一种基于锁存器实现时序收敛的方法

扫描链测试,作为一种简单、高效的可测性设计方法,已经广泛应用于集成电路设计中。该方法可以有效地检测出电路制造过程中的缺陷和故障,从而降低芯片的测试成本。但是随着扫描链的插入,芯片物理设计中的时序收敛变得更加复杂,尤其是在扫描链测试的移位模式下,由于时钟偏移的存在,保持时间可能存在大量的时序违例。针对这种情况,本文首先介绍了扫描链测试的基本原理,分析了插入扫描链之后出现保持时间违例的原因,提出了一种基于锁存器的修复时序违例的方法,并详细阐述了对于不同边沿触发的触发器组如何选择相应的锁存器实现时序收敛。最后,将该方法应用于一款电力通信芯片的物理设计,快速、高效地实现了时序的收敛。

Method of Latch Based Timing Closure

As a simple and efficient method of DFT, scan chain test has been widely used in integrated circuit design. It can effectively detect defects and faults caused in the manufacturing process, thereby reducing the cost of chip test. However, after the scan chain insertion, the timing closure of the physical design becomes more complex, especially in the shift mode. Due to the presence of clock skew, there may be a large number of hold timing violations. In view of this situation, this paper introduces the basic principles of the scan chain test and analyzes the reasons of hold timing violations after scan chain insertion. Then, a latch based method is proposed, and the way to select appropriate latches for different edge-triggered flip-flop groups is presented. Finally, the physical design of a power line communication chip is made, achieving the timing closure quickly and efficiently.