一种多线程FPGA时序驱动布线算法

随着现场可编程门阵列(FPGA)器件尺寸不断增大，计算机辅助设计(CAD)工具运行时间成为突出的问题。布线是FPGA的CAD流程中最为耗时的一个阶段，一种能有效缩短布线时间的方法就是并行布线。本文提出一种减少FPGA时序驱动布线算法运行时间的多线程方法。该算法首先将信号按照线网的扇出数量进行排序，再将排序后的线网均匀分配到各个线程中，最后并发执行所有的线程。在布线质量没有受到显著影响的前提下，即线长增加2.58%，关键路径延时增加1.78%的情况下，相对于传统通用布局布线工具(VPR)时序驱动布线算法8线程下的加速比为2.46。

A multithread FPGA timing-driven routing algorithm

As the size of Field-Programmable Gate Array(FPGA) has surged rapidly, the deteriorative runtime of Computer-Aided Design(CAD) tools has become a major concern. Routing is one of the most time-consuming stage in CAD process, while introducing parallel routing algorithm could be an effective way to cut the runtime. A multithread timing-driven routing technique based on this idea is proposed in this paper. In the parallelization approach, nets are sorted according to their fan-out amount sequence firstly, then the sorted nets are averagely assigned into threads and all the threads are executed concurrently. Using this method, the total wire length and critical path delay are increased by 2.58% and 1.78% respectively, which means the routing quality is well preserved. However, in terms of runtime, it wins approximately 2.46× speedup versus the widely used Versatile Place and Route(VPR) in the case of 8 threads.