基于FPGA的PLC 高速计数模块设计

通过对传统可编程逻辑控制器(PLC)计数模块的分析研究,介绍了基于FPGA设计的PLC高速计数模块.计数模块的核心计数部分由FPGA来完成,然后CPU通过SPI接口读取计数结果,其响应延迟只会受FPGA内部的时钟延时及外部配置电路的影响.该高速计数模块可以实现频率计数、脉冲计数、编码计数等多种不同应用场景的计数功能;同时可以实现对高频率脉冲的高精度计数并提高实时响应性.另外该模块有8路差分数字量输出,输出口可由计数结果来控制.

High speed counter in PLC based on FPGA

This paper introduces the PLC high-speed counting module based on FPGA design.The core counting part of the module is finished by FPGA,and then the CPU reads the counting result throughinterface of the SPI.The response delay will only be affected by the FPGA internal clock delay and external configuration circuit.The high-speed counting module can implement frequency counting,pulse counting,coding count and other different scenarios of the counting function and achieve high accuracy of high frequency pulse count and improve the real-time responsiveness.In addition the module has 8 differential digital outputports which can be controlled by the count results.