一种低载噪比突发扩频信号的快速捕获方法实现

针对突发扩频信号用户资源扩大、终端功率降低、系统容量提升等需求,提出了一种低载噪比突发扩频信号的快速捕获硬件实现方法。采用分段匹配滤波器加多普勒并行相干积累的方法,基于硬件实现从算法到工程进行全流程优化设计,最终实现最优的捕获性能。应用结果表明,该硬件设计实现方案的快速捕获性能优越,设计方案正确、可行,已成功应用于工程建设中。     

FPGA互连测试中的反馈桥接故障覆盖问题

现场可编程门阵列(FPGA)内部资源众多,其中互连资源出现故障的概率远远高于片内其他资源,而在以往许多互连测试研究中,所生成的测试配置存在无法覆盖反馈桥接故障的难题,所以较难有测试配置实现故障列表的100%覆盖。因此通过约束桥接故障只发生在单个查找表(LUT)内的信号线上,并结合单项函数,对反馈桥接故障模型进行优化改进,从根本上解决难题；然后对优化后的反馈桥接故障设置相应的约束条件,再使用布尔可满足性理论(SAT)生成满足约束条件的测试配置。采用优化后的故障模型对ISCAS"89基准电路进行了测试配置生成实验,结果表明生成的测试向量解决了反馈桥接故障的覆盖难题,并且在实现故障列表的100%覆盖下,优化后的故障模型所需要的测试配置数最少。     

Low-memory and high-performance architectures for the CCSDS 122.0-B-1 compression standard

Two low-memory and high-performance architectures for the CCSDS 122.0-B-1 standard are proposed. They use novel memory organizations to reduce the total memory requirements in order to be implemented in a single FPGA device. The architectures were implemented in radiation-hardened and commercial FPGA devices. Based on the experimental results for the case of Virtex5QV radiation-hardened device, the throughput is 135 MSamples/sec for image with 12 bits/pixel and horizontal resolution up 8192 pixels. Also, the proposed architectures outperform the existing one in terms of the memory requirements and area.     

Low-cost and two-cycle hardware structures of PRINCE lightweight block cipher

In this paper, low-cost and two-cycle hardware structures of the PRINCE lightweight block cipher are presented. In the first structure, we proposed an area-constrained structure, and in the second structure, a high-speed implementation of the PRINCE cipher is presented. The substitution box (S-box) and the inverse of S-box (S-box⁻¹) blocks are the most complex blocks in the PRINCE cipher. These blocks are designed by an efficient structure with low critical path delay. In the low-cost structure, the S-boxes and S-boxes⁻¹ are shared between the round computations and the intermediate step of PRINCE cipher. Therefore, the proposed architecture is implemented based on the lowest number of computation resources. The two-cycle implementation of PRINCE cipher is designed by a processing element (PE), which is a general and reconfigurable element. This structure has a regular form with the minimum number of the control signal. Implementation results of the proposed structures in 180-nm CMOS technology and Virtex-4 and Virtex-6 FPGA families are achieved. The proposed structures, based on the results, have better critical path delay and throughput compared with other's related works.     

Generating synthetic benchmark circuits for accelerated life testing of field programmable gate arrays using genetic algorithm and particle swarm optimization

Accelerated life testing (ALT) of a field programmable gate array (FPGA) requires it to be configured with a circuit that satisfies multiple criteria. Hand-crafting such a circuit is a herculean task as many components of the criteria are orthogonal to each other demanding a complex multivariate optimization. This paper presents an evolutionary algorithm aided by particle swarm optimization methodology to generate synthetic benchmark circuits (SBC) that can be used for ALT of FPGAs. The proposed algorithm was used to generate a SBC for ALT of a commercial FPGA. The generated SBC when compared with a hand-crafted one, demonstrated to be more suitable for ALT, measured in terms of meeting the multiple criteria. The SBC generated by the proposed technique utilizes 8.37% more resources; operates at a maximum frequency which is 40% higher; and has 7.75% higher switching activity than the hand-crafted one reported in the literature. The hand-crafted circuit is very specific to the particular device of that family of FPGAs, whereas the proposed algorithm is device-independent. In addition, it took several man months to hand-craft the SBC, whereas the proposed algorithm took less than half-a-day.     

Multi-resource scheduling for FPGA systems

In modern cloud data centers, reconfigurable devices (FPGAs) are used as an alternative to Graphics Processing Units to accelerate data-intensive computations (e.g., machine learning, image and signal processing). Currently, FPGAs are configured to execute fixed workloads, repeatedly over long periods of time. This conflicts with the needs, proper to cloud computing, to flexibly allocate different workloads and to offer the use of physical devices to multiple users. This raises the need for novel, efficient FPGA scheduling algorithms that can decide execution orders close to the optimum in a short time. In this context, we propose a novel scheduling heuristic where groups of tasks that execute together are interposed by hardware reconfigurations. Our contribution is based on gathering tasks around a high-latency task that hides the latency of tasks, within the same group, that run in parallel and have shorter latencies. We evaluated our solution on a benchmark of 37500 random workloads, synthesized from realistic designs (i.e., topology, resource occupancy). For this testbench, on average, our heuristic produces optimum makespan solutions in 47.4% of the cases. It produces acceptable solutions for moderately constrained systems (i.e., the deadline falls within 10% of the optimum makespan) in 90.1% of the cases.     

Model-Based Design Space Exploration for FPGA-based Image Processing Applications Employing Parameterizable Approximations

The increasing demand for low power consumption and high computational performance is outpacing available technological improvements in embedded systems. Approximate computing is a novel design paradigm trying to bridge this gap by leveraging the inherent error resilience of certain applications and trading in quality to achieve reductions in resource usage. Numerous approximation methods have emerged in this research field. While these methods are commonly demonstrated in isolation, their combination can increase the achieved benefits in complex systems. However, the propagation of errors throughout the system necessitates a global optimization of parameters, leading to an exponentially growing design space. Additionally, the parameterization of approximated components must consider potential cross-dependencies between them. This work proposes a systematic approach to integrate and optimally configure parameterizable approximate components in FPGA-based applications, focusing on low-level but high-bandwidth image processing pipelines. The design space is explored by a multi-objective genetic algorithm which takes parameter dependencies between different components into account. During the exploration, appropriate models are used to estimate the quality-resource trade-off for probed solutions without the need for time-consuming synthesis. We demonstrate and evaluate the effectiveness of our approach on two image processing applications that employ multiple approximations. The experimental results show that the proposed methods are able to produce a wide range of Pareto-optimal solutions, offering various choices regarding the desired quality-resource trade-off.     

低觉醒脑电识别与唤醒的可穿戴系统研究

为智能化地识别警戒作业人员出现的低觉醒、注意力下降的生理状态，本文介绍了一种基于FPGA和脑电信号处理的低觉醒状态检测与唤醒系统，系统通过传感器从大脑头皮采集脑电信号，转换为数字信号，经傅里叶变换获取了脑电信号的θ相对能量、α相对能量、重心频率、谱熵等4个特征量，由4个特征量表征低觉醒状态并运用支持向量机对低警戒状态进行识别，当识别出低觉醒状态时采用声音报警模块发出声音，唤醒警戒作业人员。设计系统能够较好地识别出低觉醒状态，识别率达90.8%，可为提高警戒作业工作绩效提供一种可穿戴的智能装备。     

FPGA设计的层次化实验项目的构建

数字电子技术是电子信息类的专业技术基础课程,一方面近些年可编程技术的发展及应用,改变了数字系统的设计理念、设计方法,传统的基于原理图和中小规模集成电路的设计方法已被FPGA所取代,HDL已经成为数字设计技术主流；另一方面在当前“新工科”理念下,要培养具有工程实践能力的人才,但传统工科教育的课程架构却难以满足这一要求。课程内容必须跟上时代发展,要服务社会,那么课程与教学内容的改革是无法回避的,本文以传统数字电子技术为基础,结合实际案例,从点、线、面、体四个层次设计实验项目,让学生快速入手并掌握FPGA的设计。