| 基于FPGA的宽带雷达回波信号处理板设计 |
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| 引用本文： | 顾振杰,刘宇.基于FPGA的宽带雷达回波信号处理板设计[J].国外电子测量技术,2017,36(1):74-78. |
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| 作者姓名： | 顾振杰 刘宇 |
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| 作者单位： | 中国人民解放军91336部队 秦皇岛 066000,中国人民解放军91336部队 秦皇岛 066000 |
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| 摘 要： | 对基于FPGA的宽带雷达回波信号处理板的设计方案、信号流程和芯片选型进行了研究。同时以此板卡为基础，针对回波信号模拟需求，对板卡的功能流程设计方法进行了研究，对数字瞬时测频设计、存储延时组件设计和整数倍内插等3项关键技术进行了重点阐述。设计方案可实现带宽达到1 GHz的宽带雷达回波信号的模拟，可适应脉冲压缩雷达、合成孔径雷达等新型雷达测试需求，同时，本方案对相关系统的建设具有一定的借鉴意义。
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| 关 键 词： | FPGA 回波信号 高速DA 瞬时测频 存储延时 内插 |
Design of radar echo signal processing board based on FPGA |
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| Gu Zhenjie and Liu Yu.Design of radar echo signal processing board based on FPGA[J].Foreign Electronic Measurement Technology,2017,36(1):74-78. |
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| Authors: | Gu Zhenjie and Liu Yu |
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| Affiliation: | Unit 91336 of PLA,Qinhuangdao 066000,China and Unit 91336 of PLA,Qinhuangdao 066000,China |
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| Abstract: | In this paper, the design scheme, the signal flow and the selection of the radar echo signal processing board based on FPGA are studied. In view of the demand of the echo signal simulation, the design method of the function of the board is studied. Three key technologies of the design of digital instantaneous frequency measurement and storage time delay component and integer multiple interpolation are discussed in this paper. The program can achieve 1 GHz broadband radar echo signal simulation and adapt to pulse compression radar and SAR test requirements. This project has certain reference significance to the construction of related systems. |
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| Keywords: | FPGA target echo high speed DA DIFM memory latency interpolation |
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