JPEG2000 MQ编码器的设计与实现

提出了一种JPEG2000 MQ编码器的硬件设计方案.通过状态更新超前预测、前导零检测、重归一化超前预测等方法以及字节输出的改进处理,使MQ编码器的工作速率可达1CxD/cycle.同时对各流水段中的路径进行优化改进,提高了系统的最高时钟频率.采用Verilog语言进行RTL级描述.并在Ahera的FPGA上进行了仿真验证.结果表明.在Altera的EP2S60F67214上,该MQ编码器的最高工作时钟频率可达65.19 MHz.

Design and implementation of MQ encoder in JPEG2000

This paper presented a kind of architecture of high-speed MQ enceder in JPEG2000 based on pipeline technology. To make the arithmetic coder can consume 1CxD pair per cycle, we adopted some tricks such as using the probability estimation with next state forwarding and used the method of counting the number of leading zeroes present in arithmetic results and the technology of forwarding renorm signal as well as improving the way of transferring bytes . Further more, we have modefied crucial paths in the system so that it could improve the max frequency of the enceder.The architecture is described with Verilog in RTL and implemented on Altera's FPGA. The result shows that the coder can work up to 65.19 MHz on Alters's EP2S60F67214.