基于PLB总线的H.264整数变换量化软核的设计

提出了在FPGA上实现H.264中整数变换量化的方法,设计了基于动态数据宽度和流水线技术的软核(IP),在处理速度和硬件资源方面分别进行优化。此软核作为PowerPC的一个硬件加速模块在Xilinx Virtex-ⅡPRO中进行了验证。实验表明,在目前较难使用软件方法实现高分辨率图像实时编码的情况下,本文设计的软核能够提供2110MPixels/s的编码速率,完全适应实时编码。

Hardware implementation of a PLB IP for H.264 integer transform and quantization

This paper proposes a method of realizing the integer discrete transform and quantization blocks from H.264 on FPGA and a design of IP based on dynamic data width and pipelining technology, which are optimized for processing speed and hardware resources.As a hardware accelerating module of PowerPC, this IP is verified on a Virtex-Ⅱ PRO FPGA.Under the current condition that it is difficult to use software methods to achieve real-time encoding of high-resolution images, the design presented in this paper can provide 2110M Pixel/ s encoding rate, which fully adapts to real-time coding.