一种高效的逻辑复用深度包过滤技术*

为提高检测系统的准确性,系统在数据流过滤过程中除了检查包头,还要针对载荷内容进行匹配检测,但运算量非常大,因此匹配模块的运行速度决定了入侵检测系统的性能.为此,提出了一种基于FPGA深度包过滤技术的入侵检测模型,以及一项既能减小系统规模,又能提高过滤速率的逻辑复用优化技术.

High performance deep packet filtering technology based on logic reuse

Intrusion detection system which could prevent the network resource from being attack by hackers was a new network security technology. This technology could protect system real-time. In order to improve the checking veracity, the system not only examined the packet header, but also looked though the entire payload, which was an expensive process. So the performance of the intrusion detection system depended on the speed of the match module. This paper provided a model of intrusion detection system based on the technology of deep packet filter with FPGA, then described the logic reuse optimized technique which could reduce the system dimensions as well as improve the filtering speed.