CMOS Programmable Imager Implementing Pre-Processing Operations

The CMOS Imager presented integrates a 2D photoreceptor array with a nine input analog processor on the same focal plane. The analog processor is fully programmable, performing multiply-accumulate operations. A VLSI implementation of spatial convolution operations performed on images is presented. A modified photoreceptor is presented that is based on current mode for signal transmission, thus decreasing the effect of noise on the transmitted signal and increasing the sensitivity per decade. A novel decoding scheme was used to decode the required set of photoreceptors to be presented to the analog processor. Thus only one processor unit is needed whose inputs depend on the time state. A prototype system was fabricated that incorporates 15×15 pixels in a 2×2 mm² using a 2 m double metal, single poly process.     

A Robust Analog VLSI Reichardt Motion Sensor

Silicon imagers with integrated motion-detection circuitry have been developed and tested for the past 15 years. Many previous circuits estimate motion by identifying and tracking spatial or temporal features. These approaches are prone to failure at low SNR conditions, where feature detection becomes unreliable. An alternate approach to motion detection is an intensity-based spatiotemporal correlation algorithm, such as the one proposed by Hassenstein and Reichardt in 1956 to explain aspects of insect vision. We implemented a Reichardt motion sensor with integrated photodetectors in a standard CMOS process. Our circuit operates at sub-microwatt power levels, the lowest reported for any motion sensor. We measure the effects of device mismatch on these parallel, analog circuits to show they are suitable for constructing 2-D VLSI arrays. Traditional correlation-based sensors suffer from strong contrast dependence. We introduce a circuit architecture that lessens this dependence. We also demonstrate robust performance of our sensor to complex stimuli in the presence of spatial and temporal noise.     

Synchronizable Compact CMOS Oscillator

This letter describes the design and implementation of a synchronizable compact CMOS oscillator. By using a fully differential topology, a reduction in area occupancy together with an improved robustness in front of on-chip interferences is achieved. Post-layout simulation results and experimental results for a standard CMOS 0.35 m technology are presented to validate the functionality of the tunable oscillator.     

A Modular Multi-Chip Neuromorphic Architecture for Real-Time Visual Motion Processing

The extent of pixel-parallel focal plane image processing is limited by pixel area and imager fill factor. In this paper, we describe a novel multi-chip neuromorphic VLSI visual motion processing system which combines analog circuitry with an asynchronous digital interchip communications protocol to allow more complex pixel-parallel motion processing than is possible in the focal plane. This multi-chip system retains the primary advantages of focal plane neuromorphic image processors: low-power consumption, continuous-time operation, and small size. The two basic VLSI building blocks are a photosensitive sender chip which incorporates a 2D imager array and transmits the position of moving spatial edges, and a receiver chip which computes a 2D optical flow vector field from the edge information. The elementary two-chip motion processing system consisting of a single sender and receiver is first characterized. Subsequently, two three-chip motion processing systems are described. The first three-chip system uses two sender chips to compute the presence of motion only at a particular stereoscopic depth from the imagers. The second three-chip system uses two receivers to simultaneously compute a linear and polar topographic mapping of the image plane, resulting in information about image translation, rotation, and expansion. These three-chip systems demonstrate the modularity and flexibility of the multi-chip neuromorphic approach.     

A Retinomorphic Chip with Parallel Pathways: Encoding INCREASING, ON, DECREASING, and OFF Visual Signals

Retinomorphic chips may improve their spike-coding efficiency by emulating the primate retina's parallel pathways. To model the four predominant ganglion-cell types in the cat retina, I morphed outer and inner retina microcircuits into a silicon chip, Visio1. It has 104×96 photoreceptors, 4×52×48 ganglion-cells, a die size of 9.25×9.67 mm² in 1.2 m 5 V CMOS, and consumes 11.5 mW at 5 spikes/second/ganglion-cell. Visio1 includes novel subthreshold current-mode circuits that model horizontal-cell autofeedback, to decouple spatial filtering from local gain control, and model amacrine-cell loop-gain modulation, to adapt temporal filtering to motion. Different ganglion cells respond to motion in a quadrature sequence, making it possible to detect edges of one contrast or the other moving in one direction or the other. I present results from a multichip 2-D motion system, which implements Watson and Ahumada's model of human visual-motion sensing.     

基于运动补偿的自适应时域视频降噪算法研究

视频信号内的噪声是信号中不希望出现的干扰部分,如果不加以有效的去除,会严重影响视频图像的质量.提出了一种基于运动补偿的自适应时域视频降噪算法.该方法通过运动补偿技术,在时域上跟踪并提取噪声.滤波的强度是根据物体运动轨迹上的运动强度自适应变化的.利用该算法,有效地去除了视频序列中的噪声,同时很好地保护了图像的细节.实验结果表明,采用该降噪算法处理后的视频图像质量明显优于采用空域的降噪方法的结果.     

一种基于运动补偿的时域自适应视频降噪算法

视频信号内的噪声是信号中不希望出现的干扰部分,如果不加以有效的去除,会严重影响视频图像的质量.提出了一种基于运动补偿的自适应时域视频降噪算法.该方法通过运动补偿技术,在时域上跟踪并提取噪声.滤波的强度是根据物体运动轨迹上的运动强度自适应变化的.利用该算法,有效地去除了视频序列中的噪声,同时很好地保护了图像的细节.实验结果表明,采用本文的降噪算法处理后的视频图像质量明显优于采用空域的降噪方法的结果.     

A Current-Mode Hysteretic Winner-take-all Network, with Excitatory and Inhibitory Coupling

Winner-take-all (WTA) circuits are commonly used in a wide variety of applications. One of the most used current-mode WTA designs is the one originally proposed by Lazzaro et al. [1]. Several extensions to this design have been suggested in the past. In this paper we present a variant of this current-mode WTA circuit, containing all of the enhancements previously proposed, together with new additional modifications that endow it with interesting hysteretic and lateral inhibition and excitation properties. We compare the performance of this WTA circuit to the original WTA design, providing experimental data obtained from a VLSI chip containing both types of circuits, designed using closely matched layouts. We derive analytically the response properties of the circuit's lateral diffusion network, pointing out the differences to previously proposed diffusion networks, and present experimental data confirming the theoretical predictions. We also describe application domains that can best exploit these types of hysteretic WTA circuits.     

A Pulsed Communication/Computation Framework for Analog VLSI Perceptive Systems

This paper presents the principles, the main propertiesand some applications of a pulsed communication system adaptedto the needs of the analog VLSI implementation of perceptivesystems. The system takes advantage of the fact that activitiesin perception tasks are often sparsely distributed over a largenumber of elementary processing units (cells) and facilitatesaccess to the communication channel for the more active cells.The resulting architecture can be advantageously used to setup connections between distant cells on the same chip or point-to-pointconnections between cells on different chips when direct wiringis prohibitive. Cells communicate in an asynchronous fashionwhich conserves the fine time relationships of events. The systemalso lends itself to the simple circuit implementation of typicalbiologically inspired connectivity patterns such as projectionof the activity of one cell on a region (its projective field)of the next neural processing layer, which can be on a differentchip in an actual implementation, as is the case for one of theapplications presented: an oriented-edges enhancement system.     

CMOS image sensors for sensor networks

We report on two generations of CMOS image sensors with digital output fabricated in a 0.6 μm CMOS process. The imagers embed an ALOHA MAC interface for unfettered self-timed pixel read-out targeted to energy-aware sensor network applications. Collision on the output is monitored using contention detector circuits. The image sensors present very high dynamic range and ultra-low power operation. This characteristics allow the sensor to operate in different lighting conditions and for years on the sensor network node power budget. Eugenio Culurciello (S’97–M’99) received the Ph.D. degree in Electrical and Computer Engineering in 2004 from Johns Hopkins University, Baltimore, MD. In July 2004 he joined the department of Electrical Engineering at Yale University, where he is currently an assistant professor. He founded and instrumented the E-Lab laboratory in 2004. His research interest is in analog and mixed-mode integrated circuits for biomedical applications, sensors and networks, biological sensors, Silicon on Insulator design and bio-inspired systems. Andreas G. Andreou received his Ph.D. in electrical engineering and computer science in 1986 from Johns Hopkins University. Between 1986 and 1989 he held post-doctoral fellow and associate research scientist positions in the Electrical and Computer engineering department while also a member of the professional staff at the Johns Hopkins Applied Physics Laboratory. Andreou became an assistant professor of Electrical and Computer engineering in 1989, associate professor in 1993 and professor in 1996. He is also a professor of Computer Science and of the Whitaker Biomedical Engineering Institute and director of the Institute’s Fabrication and Lithography Facility in Clark Hall. He is the co-founder of the Johns Hopkins University Center for Language and Speech Processing. Between 2001 and 2003 he was the founding director of the ABET accredited undergraduate Computer Engineering program. In 1996 and 1997 he was a visiting professor of the computation and neural systems program at the California Institute of Technology. In 1989 and 1991 he was awarded the R.W. Hart Prize for his work on mixed analog/digital integrated circuits for space applications. He is the recipient of the 1995 and 1997 Myril B. Reed Best Paper Award and the 2000 IEEE Circuits and Systems Society, Darlington Best Paper Award. During the summer of 2001 he was a visiting professor in the department of systems engineering and machine intelligence at Tohoku University. In 2006, Prof. Andreou was elected as an IEEE Fellow and a distinguished lecturer of the IEEE EDS society. Andreou’s research interests include sensors, micropower electronics, heterogeneous microsystems, and information processing in biological systems. He is a co-editor of the IEEE Press book: Low-Voltage/Low-Power Integrated Circuits and Systems, 1998 (translated in Japanese) and the Kluwer Academic Publishers book: Adaptive Resonance Theory Microchips, 1998. He is an associate editor of IEEE Transactions on Circuits and Systems I.     

A Nonlinear Noise-Shaping Delta-Sigma Modulator with On-Chip Reinforcement Learning*

The stability and quality of noise shaping is a concern in the design of higher-order delta-sigma modulators for oversampled analog-to-digital conversion. We reformulate noise-shaping modulation alternatively as a nonlinear control problem, where the objective is to find the binary modulation sequence that minimizes signal swing in a cascade of integrators operating on the difference between the input signal and the modulation sequence. Reinforcement learning is used to adaptively optimize a nonlinear neural classifier, which outputs modulation bits from the values of the input signal and integration state variables. Analogous to the pole balancing control problem, a punishment signal triggers learning whenever any of the integrators saturate. Experimental results obtained from a VLSI modulator with integrated classifier, trained to produce stable noise shaping modulation of orders one and two, are presented. The classifier contains an array of 64 locally tuned, binary address-encoded neurons and is trained on-chip with a variant on reinforcement learning.     

基于运动补偿时域滤波的视频编码算法研究

深入研究了自适应图像组结构算法,提出了一种改进方案,新方案增加了图像分组的选择范围,根据视频序列的时域变化特性,分别选择[2,2,2,2,2,2,2,2],[4,4,4,4],[8,8]和[16]四种分组模式。实验结果表明:与改进的自适应图像组结构算法相比,新方案的编码性能有所提高,而计算复杂度不变。     

A CMOS A/D Converter with Piecewise Linear Characteristic and Its Application to Sensor Linearization

A novel 8-bit CMOS A/D converter with piecewise linear characteristic is designed, implemented and tested. It can be regarded as a two-stage flash A/D converter. The resulting architecture can be applied to the linearization of nonlinear characteristics of a wide variety of sensors, just adapting the break points of the piecewise linear characteristic to get the best-fit approach to the inverse of the sensor characteristic under consideration. A very compact implementation is obtained, since two-stage A/D conversion and linearization are both performed simultaneously by the same circuit and because both A/D conversion stages share most of the required hardware. As a particular example, a sinusoidal nonlinearity, typical of several types of solid-state sensors, is compensated in this paper. Measurement results for a 2 m CMOS prototype demonstrate the validity of the proposed approach.     

A 2.4-GHz CMOS Monolithic VCO with an MOS Varactor

A 2.4-GHz CMOS VCO is presented employing pMOS transistors as voltage-controlled capacitances and on-chip hollow spiral inductors. The design was implemented in a standard digital 0.8m CMOS process and exhibits a 15% tuning range at 2.5 V supply voltage and 9 mA supply current. Phase-noise measurements show a phase-noise of about –118 dBc/Hz at 1 MHz from the carrier.     

一种用于CMOS图像传感器的新结构光电器件

提出了一种用于CMOS图像传感器的新结构光电探测器件--双极光栅场效应晶体管.通过在器件中引入pn结,有效地增加了光生电荷的读出速率,因而与传统光栅晶体管相比,双极光栅晶体管具有工作速度快、响应灵敏度高、读出电路简单等优点.     

用于低频小信号检测的CMOS放大器设计

给出了一种用于低频小信号检测的放大器的设计,从分析性能要求出发,放大器采用了二级放大结构,差分输入,实现了较高的电压增益和较好的噪声性能。设计基于无锡上华CSMC 0.6μm CMOS工艺,使用HSpice进行了仿真,仿真结果表明,在5 V的工作电压下,放大器的开环直流增益为79 dB,相位裕度为65°,单位增益带宽为80 MHz(CL=5 pF),共模抑制比为108 dB,功耗为2 mW。     

一种用于数字集成系统的新型CMOS三态缓冲器的设计

三态逻辑电路已被广泛应用于VLSI数字集成系统中.现在也有很多种实现三态逻辑的方法,但它们要么输出驱动能力不足够强要么占有较大的器件面积.在研究传统三态缓冲器的基础上设计了一种新型的三态缓冲器,据我们所知,这是使用晶体管数目最少的一种三态缓冲器结构.通过SPICE仿真实验表明,所设计的三态缓冲器与传统三态缓冲器相比具有更优的面积-延时积特性和更低的静态功耗.     

一种用于CMOS图像传感器的Column-Level模数转换器

设计了一种用于CMOS图像传感器(CIS)的column-level模数转换器(ADC)。它由一种新型斜坡发生器构成,具有分辨率可调的特点,而且以简单的结构实现了高精度和低功耗,占用较小的版图面积。基于0.35μm2P4M标准CMOS工艺,8bit ADC转换时间约50μs,最大线性误差小于±0.5LSB。在分辨率为640×480pixel的CIS中,每列共用1个比较器,提高了传感器的吞吐速率,帧频约40fps;3.3V电压下ADC总功耗不超过27mW,占用版图面积约0.5mm2。     

帧间逼近法用于大噪声红外图像的运动检测

提出一种基于像素邻域的切比雪夫逼近的方法实现运动检测。文中假定红外视频序列背景在相邻帧之间在区域上存在线性关系,由于噪声存在,这种线性方程不相容。通过在Banach空间上建立切比雪夫逼近,求出两帧之间的逼近系数,对逼近系数设定阈值,实现复杂背景的运动物体探测。通过对雨雪天气的两组数据仿真实验,并与简单帧间差模型在同等阈值下比较噪信比,发现该法鲁棒性显著提高。实验表明,该法在提取出主体运动同时,能够有效抑雨、雪等运动背景构成的噪声,具有一定应用价值。     

一种具有片上译码/放大功能的微阵列电路及其与生物纳米系统的集成

提出了一种用SMIC 0.18μm CMOS混合信号工艺实现的全集成CMOS微阵列生物芯片,并成功地实现了其与一种新的生物纳米系统的集成.该电路实现了19μm×19μm电极的4×4(16单元)阵列,反相电极.电流模式放大器,译码电路,以及逻辑控制电路的单片集成,并能够提供-1.6～1.6V的组装电压,8bit的电位分辨率及39.8dB的电流增益,电源电压为1.8V,而失调和噪声电流分别为5.9nA和25.3pArms.在实验中,利用该电路实现了对30nm聚乙烯醇包裹的磁性粒子的片上选择性组装,并对实验结果进行了讨论,从而验证了该电路的正确性和该集成方法的可行性.