三维集成电路中TSV的热特性研究

基于Comsol Multiphysics平台,通过使用有限元仿真对三维集成电路的硅通孔(TSV)模型进行了热仿真分析。分别探究了TSV金属层填充材料及TSV的形状、结构、布局和插入密度对三维(3D)集成电路TSV热特性的影响。结果表明:TSV金属层填充材料的热导率越高,其热特性就越好,并且采用新型碳纳米材料进行填充比采用传统金属材料更能提高3D集成电路的热可靠性;矩形形状的TSV比传统圆形形状的TSV更有利于3D集成电路散热;矩形同轴以及矩形双环TSV相比其他结构TSV,更能提高TSV的热特性;TSV布局越均匀,其热特性越好;随着TSV插入密度的增加,其热特性越好,当插入密度达6%时,增加TSV的数目对TSV热特性的影响将大幅减小。     

3D堆叠技术及TSV技术

介绍了3D堆叠技术及其发展现状,探讨了W2W(Wafer to wafer)及D2W(Die to wafer)等3D堆叠方案的优缺点,并重点讨论了垂直互连的穿透硅通孔TSV(Through silicon via)互连工艺的关键技术,探讨了先通孔、中通孔及后通孔的工艺流程及特点,介绍了TSV的市场前景和发展路线图。3D堆叠技术及TSV技术已经成为微电子领域研究的热点,是微电子技术及MEMS技术未来发展的必然趋势,也是实现混合集成微系统的关键技术之一。     

三维集成封装中的TSV互连工艺研究进展

为顺应摩尔定律的增长趋势,芯片技术已来到超越"摩尔定律"的三维集成时代。电子系统进一步小型化和性能提高,越来越需要使用三维集成方案,在此需求推动下,穿透硅通孔(TSV)互连技术应运而生,成为三维集成和晶圆级封装的关键技术之一。TSV集成与传统组装方式相比较,具有独特的优势,如减少互连长度、提高电性能并为异质集成提供了更宽的选择范围。三维集成技术可使诸如RF器件、存储器、逻辑器件和MEMS等难以兼容的多个系列元器件集成到一个系统里面。文章结合近两年的国外文献,总结了用于三维集成封装的TSV的互连技术和工艺,探讨了其未来发展方向。     

三维封装TSV结构热失效性分析

随着集成电路向低功耗、小体积、高集成度方向发展,二维平面集成逐渐面临挑战.硅通孔(Through Silicon Via,TSV)能够实现芯片上下垂直互连,减小引线布线长度,是三维集成技术中的关键步骤.通过有限元仿真软件(Comsol Multiphysic)对TSV-Cu模型进行了热力学仿真,对比了不同电流密度下TS...     

从专利探讨TSV发展态势

本文从TSV专利的角度,研究和探讨了TSV的发展态势。预计未来几年TSV仍是一个研究热点,专利和发展还会继续增长;美、日、韩等国际著名企业和中国台湾企业在TSV技术研究方面基础好,未来几年的竞争极有可能在这些企业之间展开;中国市场是一个庞大的市场,已经受到各大公司的青睐。中国本土企业更应该在技术和专利上大力发展,奋起猛追,争取在TSV市场能占有一席之地。     

基于FPGA的真三维显示器构建

通过介绍已制作的真三维显示器,解释了基于可视体素的显示技术.针对LED真三维显示分辨力较低的问题,采用了数字光投影的真三维显示方案,提出了基于FPGA的多机同步投影方法,实现了较高分辨力的空间可视体素显示.实验证明,该方法可保证真三维显示的实时性,降低系统对机械转台与光学元件的要求,为立体影像的互动提供了可靠的硬件基础...     

应用于MEMS封装的TSV热可靠性分析

针对MEMS系统中硅通孔(TSV)的热可靠性,利用快速热处理技术(RTP)进行了温度影响的实验分析。通过有限元分析(FEA)方法得到不同温度热处理后TSV结构的变化趋势,利用RTP对实验样品进行了不同温度的热处理实验,使用扫描电子显微镜和光学轮廓仪表征了样品发生的变化。结果表明,热处理后TSV中Cu柱的凸起程度与表面粗糙度均随热处理温度的升高而增加,多次重复热处理与单次热处理的结果基本相同。该项研究为TSV应用于极端环境下MEMS小型化封装提供了一种解决方案。     

基于FPGA的三维声学扫描平台

井下声学成像是石油勘探的一个重要领域,为便于井下声学成像算法研究,设计一种基于FPGA主控的三维声学扫描平台.平台以FPGA为控制中心,通过串口接收上位机软件指令,控制步进电机拖动声学探头,激发声波完成控声学扫描,实现不同声学处理算法处理下的高精度可控声学成像.     

基于FPGA的LED体三维显示方案研究

基于人眼视觉暂留特性及LED的高速发光特性,设计了一套LED体三维显示系统.首先利用Matlab生成三维数据,通过红外模块传输到显示驱动电路;其次快速旋转LED阵列,由角度编码器获取旋转角度值,并根据角度值计算对应的二维截面图形;最后通过调制LED的发光与消隐实现相应的显示.该系统基于24×16二维LED阵列,具有69 120个体像素,实现了空间尺寸为φ94.4 mm×66.8 mm的稳定柱体内三维显示.     

基于TSV的三维集成螺旋电感等效电路模型

基于硅通孔(TSV)技术,可以实现微米级三维无源电感的片上集成,可应用于微波/射频电路及系统的微型化、一体化三维集成。考虑到三维集成电路及系统中复杂、高密度的电磁环境,在TSV电感的设计和使用中,必须对其电路性能及各项参数指标进行精确评估及建模。采用解析方法对电感进行等效电路构建和寄生参数建模,并通过流片测试对模型进行了验证。结果表明,模型的S参数结果与三维仿真结果吻合良好,证实了等效电路构建的精确性。采用所建立的等效电路模型可以提高TSV电感的设计精度和仿真效率,解决微波电路设计及三维电磁场仿真过程中硬件配置要求高、仿真速度慢等问题。     

Fabrication of Silicon Carriers With TSV Electrical Interconnections and Embedded Thermal Solutions for High Power 3-D Packages

This paper presents micro fabrication process and wafer-level integration of a silicon carrier, which consists of two Si chips that are bonded together with evaporated AuSn-solder. There are micro fins and channels fabricated in the Si chip and form the embedded cooling layer after bonding. The embedded cooling layer is connected with an inlet and an outlet to form a fluidic path for heat transfer enhancement. Besides, in the silicon carrier, there are through silicon vias (TSVs) with metal film on sidewall for electrical interconnection. Two or more carriers can then be stacked together with a silicon interposer in between to make up of a stacked cooling module for high power heat dissipation. The advantage of this 3-D stacking method is that it provides a method of simultaneously realizing electrical interconnection and fluidic path and it can extract heat from the constraints of 3-D silicon module chips to surface without external liquid circulation.     

Designing a 3-D FPGA: Switch Box Architecture and Thermal Issues

Three-dimensional (3-D) integration is an attractive technology to reduce wirelengths in a field-programmable gate array (FPGA). However, it suffers from two problems: one, the inter-layer vias are limited in number, and second, the increased power density leads to high junction temperatures. In this paper, we tackle the first problem by designing switch boxes that maximize the use of the vias. Compared to the previously used subset switch box, our best switch box reduces the number of vias by about 49% and area-delay product by about 9%. For the second problem, we utilize the difference in power densities between CLBs and some of the hard blocks in modern FPGAs to distribute the power more uniformly across the FPGA. The peak temperature in a two-layer FPGA reduces by about 16degC after our change.     

3DIC集成与硅通孔(TSV)互连

介绍了3维封装及其互连技术的研究与开发现状,重点讨论了垂直互连的硅通孔（TSV）互连工艺的关键技术及其加工设备面临的挑战．提出了工艺和设备开发商的应对措施并探讨了3DTSV封装技术的应用前景。     

Stacked 3-D Fin-CMOS technology

A stacked three-dimensional Fin-CMOS (SF-CMOS) technology has been proposed and implemented. The technology is based on a double-layer SOI wafer formed by performing two oxygen implants to form two single-crystal silicon films with isolation layer in between. The proposed approach achieves a 50% area reduction and significant shortening of wiring distance between the active devices when compared with existing planar CMOS technology. The SF-CMOS technology also inherits the scalability and two-dimensional processing compatibility of the FinFET architecture.     

三维显示技术的探索

我们绝大多数人所看到的世界都是三维的,而所触及的几乎所有介质,无论是印刷的、照片或影像,都是二维的.     

The Thermal Stress Analysis for IC Integrations with TSV Interposer by Complement Sector Models

The thermal stress of typical integrated circuit (IC) integration with the interposer of through silicon via (TSV) was investigated in this study. To overcome the huge computational costs due to meshing the large amount of TSVs’ microstructures, a simplified method, i.e. the complement sector model, was proposed and verified by the symmetric 1/8th full model. Using the sector model, the parametric studies were carried out to reveal the critical locations of TSV and the crucial parameters. Furthermore, statistical methods were invoked to clarify the impact of the major parameters, such as the modulus and coefficient of thermal expansion of underfill materials, the pitch and diameter of TSV, etc. Upon the analysis results, the design of minimized stress in TSV for the IC integration with TSV interposer was achieved.     

三维TPC译码器的设计及FPGA实现

Turbo乘积码（TPC）是一种性能优秀的纠错编码方法,它具有译码复杂度低、译码延时小等优点,且在低信噪比下可以获得近似最优的性能。介绍了基于Chase算法的三维TPC软输入软输出（SISO）迭代译码算法,提出了三维TPC译码器硬件设计方案并在FPGA芯片上进行了仿真和验证。测试结果表明,该译码器具有较高的纠错能力,满足移动通信误码率的要求。     

Analytical solution on interfacial reliability of 3-D through-silicon-via (TSV) containing dielectric liner

Interfacial reliability is a challenging issue in through-silicon-via (TSV) technique. To accurately investigate the interfacial reliability of TSV, this paper developed an analytical solution approach, in which the effects of the liner are considered. The validity of the analytical solution is executed by comparison with finite element simulation results. Results show that two approaches have good agreement, with a deviation within 10%, illustrating the validity of the analytical solution developed in this study. Then, using the developed analytical solution, the effects of via diameter, the liner thickness, and the liner materials of TSV on interfacial reliability are investigated with the steady-state energy release rate (ERR). Analytical results show that the steady-state ERR is not only determined by the coefficient of thermal expansion (CTE) mismatch between adjacent materials, but also affected by the products (E × CTE²) of Young’s modulus (E) and CTE² of the liner. Liner materials with lower E × CTE² values will lead to lower steady-state ERR. Additionally, the combined effects of copper via diameter and liner thickness on ERR declare that the ERR highly depends on copper via diameter.     

Low Thermal Budget Processing for Sequential 3-D IC Fabrication

Laser annealing can be used for electrical activation of dopants without excessively heating the material deeper within the work piece. The authors demonstrate that laser annealing could be used for activating the dopants in the upper levels of an exemplary 3-D integrated circuit structure without affecting the operation of the devices below. We then use a 450 degC low-temperature oxide deposition process for forming the gate oxide and laser annealing for activating the dopants at the source/drain and gate regions to fabricate CMOS transistors. This process can be used to fabricate the transistors on the upper levels of a general 3-D IC structure without affecting the quality of the devices below