Impact of Aging on the Reliability of Delay PUFs

Physically Unclonable Functions (PUFs) are mainly used for generating unique keys to identify electronic devices. These entities mainly benefit from the process variations occurring during the device manufacturing. To be able to use PUFs to identify electronic devices or to utilize them in cryptographic applications, the reliability of PUFs needs to be assured under a wide variety of environmental conditions and aging mechanisms, including the switching activity of the PUFs’ internal signals. In practice, it is important to evaluate aging effects as early as possible, preferentially at design time. In this paper, we evaluate the impact of aging on two types of delay-PUFs (arbiter-PUFs and loop-PUFs) with different switching activities. This work takes advantage of both simulation tool and silicon tests on a 65nm ASIC implementation. To expedite the simulation process and get rid of conducting simulations of multiple delay-element PUFs, we propose an extrapolation method to evaluate the effect of BTI (Bias Temperature-Instability) and HCI (Hot Carrier Injection) aging under different switching activities on PUFs with multiple delay elements using the aging effects on single delay-element PUFs. The results show that switching activity (expressed in terms of transitions/time) has a limited impact on delay chains of considered delay-PUFs, while it has a greater impact on the arbiter (RS latch) of the arbiter-PUF. The simulation results show that the aging-related Bit Error Rate in an arbiter-PUF with high switching activity can be 11 times worse than the Bit Error Rate in the same PUF when there is no activity in 20 months.     

FPGA-based Physical Unclonable Functions: A comprehensive overview of theory and architectures

Physically Unclonable Functions (PUFs) are a promising technology and have been proposed as central building blocks in many cryptographic protocols and security architectures. Among other uses, PUFs enable chip identifier/authentication, secret key generation/storage, seed for a random number generator and Intellectual Property (IP) protection. Field Programmable Gate Arrays (FPGAs) are re-configurable hardware systems which have emerged as an interesting trade-off between the versatility of standard microprocessors and the efficiency of Application Specific Integrated Circuits (ASICs). In FPGA devices, PUFs may be instantiated directly from FPGA fabric components in order to exploit the propagation delay differences of signals caused by manufacturing process variations. PUF technology can protect the individual FPGA IP cores with less overhead. In this article, we first provide an extensive survey on the current state-of-the-art of FPGA based PUFs. Then, we provide a detailed performance evaluation result for several FPGA based PUF designs and their comparisons. Subsequently, we briefly report on some of the known attacks on FPGA based PUFs and the corresponding countermeasures. Finally, we conclude with a brief overview of the FPGA based PUF application scenarios and future research directions.     

A PUFs-based hardware authentication BLAKE algorithm in 65 nm CMOS

This paper presents a hardware authentication BLAKE algorithm based on physical unclonable functions (PUFs) in Taiwan Semiconductor Manufacturing Company low-power 65 nm CMOS. To support hardware authentication feature, PUFs have been organised in BLAKE algorithm as the salt value. The trials table method is used to improve the robust of PUFs, resulting in approximately 100% stability against supply voltage variations form 0.7 V to 1.6 V. By discussing the G-function of BLAKE algorithm, the hardware implementation is considered for acceleration, resulting in significant performance improvements. The die occupies 2.62 mm² and operates maximum frequency 1.0 GHz at 1.6 V. Measured results show that PUFs have great random characteristic and the authentication chip dissipates an average power of 91 mW under typical condition at 1.2 V and 780 MHz. In comparison with other works, the PUFs-based BLAKE algorithm has hardware authentication feature and improves throughput about 45%.     

Flexible and Biocompatible Physical Unclonable Function Anti-Counterfeiting Label

Optical physical unclonable functions (PUFs) have been proven to be one of the most effective anti-counterfeiting strategies. However, optical PUFs endowed with flexibility and biocompatibility have not been developed, limiting their application scenarios. Herein, biocompatible and flexible optical PUF labels are developed by randomly embedding microdiamonds in silk fibroin films. The PUF labels can be conformally attached onto the surface of complex shaped objects, providing the desired protection against fake and interior products. In this system, silk fibroin films serve as a flexible and biocompatible substrate, while the Raman signal of the microdiamonds serves as response of the excitation. The extremely high stability and random distribution of the microdiamonds ensure the performance of PUFs, and the maximum encoding capability of 2¹⁰⁰⁰⁰ is finally realized. The cytotoxicity analysis results also verify the biosafety of the PUF system. In addition, the as-prepared PUF labels are attached onto the surface of polyethylene material, and human skin, and even have been implanted under chicken skin tissue, promising their practical applications.     

Extracting secret keys from integrated circuits

Modern cryptographic protocols are based on the premise that only authorized participants can obtain secret keys and access to information systems. However, various kinds of tampering methods have been devised to extract secret keys from conditional access systems such as smartcards and ATMs. Arbiter-based physical unclonable functions (PUFs) exploit the statistical delay variation of wires and transistors across integrated circuits (ICs) in manufacturing processes to build unclonable secret keys. We fabricated arbiter-based PUFs in custom silicon and investigated the identification capability, reliability, and security of this scheme. Experimental results and theoretical studies show that a sufficient amount of inter-chip variation exists to enable each IC to be identified securely and reliably over a practical range of environmental variations such as temperature and power supply voltage. We show that arbiter-based PUFs are realizable and well suited to build, for example, key-cards that need to be resistant to physical attacks.     

Organic physically unclonable function on flexible substrate operable at 2 V for IoT/IoE security applications

We fabricated organic ring oscillators (ROs) on a flexible substrate and utilized them as the core circuit of a physically unclonable function (PUF). An RO-PUF is a security primitive that generates unique identification numbers (IDs) by extracting the frequency variation of the RO. We fabricated two RO-PUFs and evaluated their IDs in terms of stability and uniqueness at various operating voltages. The experimental results indicate that our RO-PUFs have a high degree of uniqueness and exhibit good stability relative to voltage fluctuations with a nominal operating voltage below 2 V.     

Design and implementation of an improved MA‐APUF with higher uniqueness and security

An arbiter physical unclonable function (APUF) has exponential challenge‐response pairs and is easy to implement on field‐programmable gate arrays (FPGAs). However, modeling attacks based on machine learning have become a serious threat to APUFs. Although the modeling‐attack resistance of an MA‐APUF has been improved considerably by architecture modifications, the response generation method of an MA‐APUF results in low uniqueness. In this study, we demonstrate three design problems regarding the low uniqueness that APUF‐based strong PUFs may exhibit, and we present several foundational principles to improve the uniqueness of APUF‐based strong PUFs. In particular, an improved MA‐APUF design is implemented in an FPGA and evaluated using a well‐established experimental setup. Two types of evaluation metrics are used for evaluation and comparison. Furthermore, evolution strategies, logistic regression, and K‐junta functions are used to evaluate the security of our design. The experiment results reveal that the uniqueness of our improved MA‐APUF is 81.29% (compared with that of the MA‐APUF, 13.12%), and the prediction rate is approximately 56% (compared with that of the MA‐APUF (60%‐80%).     

Integrated circuit design for physical unclonable function using differential amplifiers

A physical unclonable function (PUF) based on process variations on silicon wafers is a very promising technology which finds various applications in identification and authentication, but only a few integrated circuits have been reported so far. As those circuits are vulnerable to power supply noises, switching noises and environmental variations, they lead to a reliability issue such as time-varying or metastable responses. To resolve this issue, this letter proposes a new integrated circuit design for PUFs using differential amplifiers. The feasibility of the proposed circuit has been theoretically analyzed and validated through HSPICE simulations for the previous and proposed circuits.     

Reliability optimization of analog integrated circuits considering the trade-off between lifetime and area

The reliability of analog integrated circuits becomes a major concern for the semiconductor industry as technology continuously scales. Among the many contributing factors, manufacturing process induced parameter variations and lifetime operational-condition-dependent transistor aging are two major hurdles limiting the reliability of analog circuits. Process variations mainly influence the parametric yield value of the fresh circuits, while transistor aging due to physical effects, such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI), will cause another yield loss during circuit lifetime. In the past decades, the two issues were mainly studied separately by various communities, but analog designers nowadays need an accurate yet efficient method to analyze and optimize their circuits during the design phase, to ensure a more robust design tolerant of such joint effects.This paper proposes an efficient method for sizing of analog circuits for reliability. It is based on the analysis and optimization of the fresh worst-case distance value for each circuit performance, which can be used to characterize the robustness of circuits considering process variations and aging effects in terms of x-sigma. The fresh and aged sizing rules as well as the maximum area constraints are checked during the optimization. The trade-off between the circuit lifetime and the price we pay in terms of layout area is studied in detail. According to the result of this trade-off analysis, a longer circuit lifetime requires more total area to be spent in layout, and designers can ensure the circuit robustness with certain layout area consumption.     

Process Variations-Aware Statistical Analysis Framework for Aging Sensors Insertion

As process technology continues to shrink, Process Variations and Aging effects have an increasing impact on the reliability and performance of manufactured circuits. Aging effects, namely due to Negative Bias Temperature Instability (NBTI) produce performance degradation as time progresses. This degradation rate depends on a) Operational conditions (e.g., V_DD, Temperature and time of electrical stress on MOS transistors) and b) Static technological parameters defined in the fabrication process. Moreover, performance of electronic systems for safety-critical applications which operate for many years in harsh environments are more prompt to be impacted by aging. In order to guarantee a safe operation in advanced technologies, aging monitoring should be performed on chip using built-in aging sensors. The purpose of this work is to present a methodology to determine the correct location for aging sensor insertion, considering the combined impact of process variations (PV) and aging effects (namely due to NBTI). In order to implement the methodology, a path-based statistical timing analysis framework and tools have been developed. It is shown that delay path reordering, associated with PV and aging, may justify the insertion of a few additional sensors, to cover abnormal delays of signal paths that become critical, under long system operation (e.g., 10 years).     

Aging comparative analysis of high-performance FinFET and CMOS flip-flops

This paper presents a comparative performance analysis to investigate the impact of aging mechanisms on various flip-flops in CMOS and FinFET technologies. We consider Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) effects on the robustness of high performance flip-flops. To apply BTI and HCI aging mechanisms, we utilize long-term model to estimate ∆ V_th and employ the updated V_th in transistor model file. The simulation results on performance analysis indicate the high ranking of various flip-flops considering speed and power consumption in each CMOS and FinFET technologies, moreover, approve the superiority of static FinFET flip-flops over CMOS flip-flops. In addition, a comparative analysis considering temperature and V_DD variations over different FinFET flip-flop structures demonstrates the average percentages of T_DQmin and PDP degradation against aging mechanisms are significantly less than similar CMOS flip-flops.     

Unpredictably Disordered Distribution of Hetero-Blended Graphene Oxide Flakes with Non-Identical Resistance in Physical Unclonable Functions

In this study, a new concept of physical unclonable functions (PUFs) is introduced comprising reduced graphene oxide (GO) materials. To create a disordered conductivity distribution, two types of GO are used: HGO, are produced by the conventional Hummers’ method, and PGO, produced by Brodie's method with an additional unique purification procedure. It is found that PGO becomes graphene-like after room-temperature chemical reduction. These two reduced GOs have a distinct conductivity difference of up to 10⁴ times. By blending these two materials, a random mixture is created that can generate a highly unpredictable electrical signal, serving as an ideal security key with strong randomness and uniqueness. The optimized PUF device, based on this approach, demonstrates excellent performance in generating secure keys.     

Reconfigurable Electronic Physically Unclonable Functions Based on Organic Thin-Film Transistors with Multiscale Polycrystalline Entropy for Highly Secure Cryptography Primitives

In this study, organic thin-film transistors (OTFTs) are investigated as a promising platform for cost-effective, reconfigurable, and strong electronic physically unclonable functions (PUFs) for highly secure cryptography primitives. Simple spin-casting of solution-processable small-molecule organic semiconductors forms unique and unclonable fingerprint thin films with randomly distributed polycrystalline structures ranging from nanoscale molecular orientations to microcrystalline orientations, which provides a stochastic entropy source of device-to-device variations for OTFT arrays. Blending organic semiconductors with polymer materials is a promising strategy to improve the reliability of OTFT-based PUFs. Studies on the relationship between the phase-separated polycrystalline microstructure of organic semiconductor/polymer blend films and PUF characteristics reveal that the 2D mosaic microcrystalline structure of organic semiconductors in the vertically phase-separated trilayered structure enables the implementation of OTFT-based PUFs that simultaneously satisfy the requirements of being unclonable and unpredictable, with reliable cryptographic properties. The inherent multiscale randomness of the crystalline structure allows random distribution in OTFT-based PUFs even with various channel dimensions. The secret bit stream generated from the OTFT-based PUF developed in this study is reconfigurable by simply changing the gate bias, demonstrating the potential to counter evolving security attack threats.     

Hybrid Digital-Analog Relaying for Cooperative Transmission Over Slow Fading Channels

Hybrid digital-analog coding schemes have been proposed in source-channel coding to increase the robustness toward channel mismatch, in the absence of transmitter channel state information (CSIT). Recognizing that the same kind of robustness is needed at the relay in a three-node relay network, we propose several novel relaying protocols based on hybrid digital-analog transmission. We compare the performance of the new schemes with traditional digital-only (decode-and-forward or compress-and-forward) or analog-only (amplify-and-forward) relaying, as well as to performance bounds corresponding to genie-aided compress-and-forward relaying. Our new protocols achieve significant gains in terms of achievable expected rates, and they are able to close in on the performance bounds. In particular, we conclude that the best overall performance is obtained by an adaptive combination of decode-and-forward and hybrid digital-analog relaying.      

Robust proportionate adaptive filter based on maximum correntropy criterion for sparse system identification in impulsive noise environments

Proportionate-type adaptive filtering (PtAF) algorithms have been successfully applied to sparse system identification. The major drawback of the traditional PtAF algorithms based on the mean square error (MSE) criterion show poor robustness in the presence of impulsive noises or abrupt changes because MSE is only valid and rational under Gaussian assumption. However, this assumption is not satisfied in most real-world applications. To improve its robustness under non-Gaussian environments, we incorporate the maximum correntropy criterion (MCC) into the update equation of the PtAF to develop proportionate MCC (PMCC) algorithm. The mean and mean square convergence performance analysis are also performed. Simulation results in sparse system identification and echo cancellation applications are presented, which demonstrate that the proposed PMCC exhibits outstanding performance under the impulsive noise environments.     

Simulation-based evaluation of probing attacks to arbiter PUFs using a time-resolved emission microscope

Probing attacks to arbiter PUFs (physical unclonable functions) using a time-resolved emission microscope are evaluated by simulation. It is assumed that signal delay in the arbiter PUF chip is measured directly by using a time-resolved emission microscope. Only two challenge inputs are required to do that. A simple procedure can predict the response of the arbiter PUF. The relationship between the rate of successful response estimation and the accuracy of signal timing measurement is evaluated by simulation. The simulated results show the rate of successful response estimation is 70% when the accuracy is around 30 ps. A time resolution of 12.5 ps has been achieved by the commercial time-resolved emission microscope, so that this result shows the feasibility of the probing attacks to arbiter PUFs using a time-resolved emission microscope.     

一种新型多目发送保序机制及实现

本文提出了一种双层多中心多目发送保序机制，并在以太网和工作站环境中实现．通过将本方法与现有集中式、分布式和树型方式的比较以及对实验数据的分析，认为集中式虽然通信开销低、简单易实现，但坚定性差、并行度低；分布式方式虽然坚定性强，但并行度低、通信开销大、效率低；传播树方式效率虽然较前两种有所提高，但在根结点处同样并行度低、坚定性差，而且结构不灵活．本文提出的方法，避免了上述三种方式的缺点，并且具有坚定性强、并行度高和结构灵活、简单的特点．     

Analysis of 6 T SRAM cell in sub-45 nm CMOS and FinFET technologies

The semiconductor industry is exploring technology scaling to pursuit the Moore's Law. The actual processors operation frequency grows the need for fast memories. Nowadays, SRAM cells occupy a considerable area in VLSI designs. Several challenges follow this performance improvement achieved at each new technology node. The Process, Voltage, and Temperature (PVT) variability, aging effects due to BTI influence and radiation-induced Single-Event Upset (SEU) are three relevant issues on the SRAM nanometer design. The main contribution of this work is to present a panorama of these effects on SRAM as technology scaling. The most frequently used SRAM cell, the 6 T, is evaluated from 45 nm to 7 nm bulk CMOS and FinFET technologies. Results observed the effects on delay, power, and noise margins, showing that process variability can introduce up to 100% of power deviation. Read Static Noise Margin (RSNM) presents about 20% of deviation under process variability and the cell noise robustness is reduced dramatically in worst cases. FinFET technology and high-performance models show more robustness against radiation. SRAM cells with low-power devices demonstrated more sensitive to delay degradation due to aging effects.     

A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28 nm FDSOI

Due to the process variation, Spin Transfer Torque Magnetic Tunnel Junction (STT-MTJ) faces great challenges in fabrication process. Meanwhile, its neighbor CMOS is also influenced by significant process variation with the continuous technology scaling down. Both of the two effects lead to degraded performance of hybrid MTJ/CMOS circuit. This paper proposes a methodology to alleviate the impact of process variation on the performance of MTJ based applications. The methodology is presented by carrying out a novel design of non-volatile flip-flop (NVFF) using asymmetrical forward body bias (FBB) in fully depleted silicon on insulator (FDSOI). Simulation results show that the sensing errors have been almost removed by this method with the minimum size of circuit. In addition, the thermal robustness of this circuit has also been dramatically improved.     

8T vs. 6T SRAM cell radiation robustness: A comparative analysis

We analyze and compare the impact of radiation-induced transient effects based on evaluating the critical charge parameter for 6T and 8T SRAMs during hold, read and write operations. Results on a commercial 65 nm CMOS technology show that 6T and 8T cells offer quite similar robustness when they are in hold. However, the critical charge observed in other operation modes is reduced a 55% respect to the hold operation. For this reason, we provide a thorough analysis of the critical charge behavior in 6T and 8T SRAMs to determine the dependence of memory radiation robustness with memory state. Single event upsets and single event transients have been considered in the analysis, showing that 8T have better performance than 6T. The dependence of critical charge with memory state for high workload memories modifies the overall memory SER estimation indicating the significance of analyzing the memory robustness as a memory state function. In general, the SER estimation results show that the robustness behavior of 8T-based cells is better than robustness behavior of 6T-based cells.