基于预计算的Viterbi译码器ACS单元低功耗设计

提出了将预计算方法用于Viterbi译码器ACS单元的设计中，根据所选输入，预先计算出加比选结果，避免全部输入参与运算；通过减少电路开关行为的方式，达到降低功耗的目的。该方法适用于能量受限的电路，如无线传感器网络节点及便携式通信设备等。     

低功耗内容寻址存储器的设计

分析了传统内容寻址存储器(CAM)结构,提出其功耗模型。根据功耗模型,设计了一种适用于以太网MAC地址识别的新型低功耗CAM单元结构及其预充电路。基于SMIC 0.18μm/1.8V工艺库,利用HSPICE平台对电路进行仿真,仿真频率为100MHz。结果表明,64×64的新型CAM阵列平均查找时间为0.8955ns,写入功耗和查找功耗分别为22.61μW/b和4.186μW/b,仅为传统CAM结构的12.58%和37.9%。     

Low-Power Ternary Content-Addressable Memory Design Using a Segmented Match Line

Power consumption in match lines is the most critical issue for low-power ternary content-addressable memory (TCAM) designs. In the proposed match-line architecture, the match line in each TCAM word is partitioned into four segments and is selectively pre-charged to reduce the match-line power consumption. The partially charged match lines are evaluated to determine the final comparison result by sharing the charges deposited in various parts of the partitioned segments. This arrangement reduces the match-line power consumption by reducing effective capacitor loading and voltage swing at match lines. The segmented architecture also enhances operational speed by evaluating multiple segments in parallel and by overlapping the pre-charging and evaluation stages. 512 $times$ 72 TCAM is designed using 0.18-$mu{hbox {m}}$ CMOS technology. The extracted RC values are used to show the power reduction benefits. The sample design demonstrated that the match-line power consumption using a segmented match line was conservatively 44% of that produced by traditional parallel TCAM. The power savings by segmenting match lines can be up to 41% over a low-voltage swing technique due to the independent discharge capability in segmented match-line architecture.      

一种低功耗异步FIFO存储器的设计

针对传统异步FIFO功耗较高的缺点,设计一种低功耗异步FIFO存储器。通过采用对异步读写指针的前两个状态位直接比较的方法,减少格雷码向二进制转换的电路,并增加门控时钟电路,从而大大降低了存储器的动态功耗。通过软件QuartusⅡ7.2对其进行功耗估算,功耗降低了8%。用ModelSim SE 6.1b进行仿真,验证了设计功能的正确性。     

一种低压低功耗SRAM/SOI单元设计

提出一种改进4管自体偏压结构SRAM/SOI单元.基于TSUPREM4和MEDICI软件的模拟和结构性能的分析,设计单元结构并选取结构参数.该结构采用nMOS栅下的含p+埋沟的衬底体电阻代替传统6管CMOSSRAM单元中的pMOS元件,具有面积小、工艺简单的优点.该结构可以在0.5V的电源电压下正常工作,与6管单元相比,该单元瞬态响应正常,功耗只有6管单元的1/10,满足低压低功耗的要求.     

一种低压低功耗SRAM/SOI单元设计

提出一种改进4管自体偏压结构SRAM/SOI单元.基于TSUPREM4和MEDICI软件的模拟和结构性能的分析,设计单元结构并选取结构参数.该结构采用nMOS栅下的含p 埋沟的衬底体电阻代替传统6管CMOSSRAM单元中的pMOS元件,具有面积小、工艺简单的优点.该结构可以在0.5V的电源电压下正常工作,与6管单元相比,该单元瞬态响应正常,功耗只有6管单元的1/10,满足低压低功耗的要求.     

A Low Power SRAM/SOI Memory Cell Design

提出一种改进4管自体偏压结构SRAM/SOI单元. 基于TSUPREM4和MEDICI软件的模拟和结构性能的分析，设计单元结构并选取结构参数. 该结构采用nMOS栅下的含p+埋沟的衬底体电阻代替传统6管CMOS SRAM单元中的pMOS元件，具有面积小、工艺简单的优点. 该结构可以在0.5V的电源电压下正常工作，与6管单元相比，该单元瞬态响应正常，功耗只有6管单元的1/10，满足低压低功耗的要求.     

Multi-Module Multi-Port Memory Design for Low Power Embedded Systems

In this paper we describe a multi-module, multi-port memory design procedure that satisfies area and/or energy constraints for embedded applications. Our procedure consists of application of loop transformations and reordering of array accesses to reduce the memory bandwidth followed by memory allocation and assignment procedures based on ILP models and heuristic-based algorithms. The specific problems include determination of (a) the memory configuration with minimum area, given the energy bound, (b) the memory configuration with minimum energy, given the area bound, (c) array allocation such that the energy consumption is minimum for a given memory configuration (number of modules, size and number of ports per module). The results obtained by the heuristics match well with those obtained by the ILP methods.     

Memory Design and Exploration for Low Power, Embedded Systems

In this paper, we describe a procedure for memory design and exploration for low power embedded systems. Our system consists of an instruction cache and a data cache on-chip, and a large memory off-chip. In the first step, we try to reduce the power consumption due to memory traffic by applying memory-optimizing transformations such as loop transformations. Next we use a memory exploration procedure to choose a cache configuration (cache size and line size) that satisfies the system requirements of area, number of cycles and energy consumption. We include energy in the performance metrics, since for different cache configurations, the variation in energy consumption is quite different from the variation in the number of cycles. The memory exploration procedure is very efficient since it exploits the trends in the cycles and energy characteristics to reduce the search space significantly.     

低功率高压电源的模块化设计

随着现代雷达技术的飞速发展，以及现代雷达对缩短研制周期、提高可维护性和可靠性的要求，小型化、模块化已经成为现代雷达技术发展的方向。作为雷达发射机关键部分的高压电源必须进行模块化设计，提高效率和可维护性以及可靠性，减小体积和重量，以适应现代雷达的要求，本文重点介绍低功率高压电源的模块化设计。     

一种低电压低功耗的甲乙类S2I存储单元

提出了一种低电压、低功耗的甲乙类S2I存储单元,电源电压为±0.5V。电路采用CMOS开关以增大输入信号动态范围,使用交叠时钟控制方案以改善性能。使用EKVMOS晶体管模型参数进行了电路仿真,仿真结果表明该电路的性能优于基本甲乙类存储单元。文中也给出了基于该存储单元的通用积分器电路。     

一种新型低功耗加固SRAM存储单元

提出了一种抗辐射加固12T SRAM存储单元.采用NMOS管组成的堆栈结构降低功耗,利用单粒子翻转特性来减少敏感节点,获得了良好的可靠性和低功耗.Hspice仿真结果表明,该加固SRAM存储单元能够完全容忍单点翻转,容忍双点翻转比例为33.33％.与其他10种存储单元相比,该存储单元的面积开销平均增加了 3.90％,功...     

低功耗VLSI芯片的设计方法

对便携式电子器件的日益需求已经导致了功耗在IC设计产业的重要性。根据VLSI的设计流程,结合微处理器的工作机制,在系统、行为、结构、逻辑和物理5个层面上对低功耗的设计方法做了全面地分析。     

Reduced Memory and Low Power Architectures for CORDIC-based FFT Processors

This paper presents a pipelined, reduced memory and low power CORDIC-based architecture for fast Fourier transform implementation. The proposed algorithm utilizes a new addressing scheme and the associated angle generator logic in order to remove any ROM usage for storing twiddle factors. As a case study, the radix-2 and radix-4 FFT algorithms have been implemented on FPGA hardware. The synthesis results match the theoretical analysis and it can be observed that more than 20% reduction can be achieved in total memory logic. In addition, the dynamic power consumption can be reduced by as much as 15% by reducing memory accesses.     

一种低功耗无电容型LDO的设计

提出了一种片上集成的低功耗无电容型LDO(low drop out)电路。该电路采用折叠型cascode运放作为误差放大器,通过消除零点的密勒补偿技术提高了环路稳定性;并在电路中加入了一种新的限流保护结构以保证输出电流过大时对LDO的输出进行保护。此外,在电路中加入了省电模式,可在保持LDO输出1.8 V情况下节省大于70%的功耗。该设计采用HHNEC 0.13μmCMOS工艺,仿真结果显示:在2.5~5.5 V电源供电、各个工艺角及温度变化条件下,LDO输出的线性调整率小于2.3 mV/V,负载调整率小于14μV/mA,温度系数小于27×10-6/℃;在正常工作模式下,整个LDO消耗85μA电流;在省电模式下仅消耗23μA电流。     

嵌入式系统的低功耗设计技术

随着嵌入式系统的广泛应用,低功耗问题摆在了设计人员面前.低功耗设计包括系统设计、硬件设计、软件设计、器件的工艺设计等诸多方面.其中器件的工艺设计主要由半导体器件的厂家来完成,嵌入式系统的应用设计人员只需要关心器件的功耗指标,更多的工作集中于系统的硬件、软件以及它们之间的配合方面.本文主要从这些方面讨论嵌入式系统的低功耗设计问题和设计方法.     

折叠控制器的低功耗改进设计

文章提出了一种硬件开销小的降低测试功耗的折叠控制器设计方案,该设计方案在原有折叠控制器的基础上只需对其中的折叠索引计数器进行改进设计,从而得到伪单输入跳变的测试向量集,达到降低待测电路功耗的目的。     

低功耗LNA设计

为了应对低功耗电路设计要求,提出了一个在低功耗要求下CMOS低噪声放大器的设计方法。使用该方法在0.18μm CMOS集成工艺下,设计一款低噪声放大器,并在ADS中进行前仿真。     

一种低功耗低温漂振荡器的设计

基于0.15 μm BCD工艺,提出了一种低功耗低温漂振荡器。分析了环形振荡器的振荡频率温度漂移特性,采用翻转电平优化技术,结合短路电流控制技术,获得了低温度漂移的振荡频率。且电流消耗极低。该振荡器适用于锂电池保护监测芯片。测试结果表明,在-40 ℃~100 ℃温度范围、32 kHz振荡频率、5 V电源电压条件下,该振荡器的振荡频率随温度的变化率小于3.3%,电流消耗仅为170 nA。     

低功耗CMOS低噪声放大器的设计

针对低功耗电路设计的需求,提出了一种低功耗约束下CMOS低噪声放大器的设计方法,并与传统的设计方法进行了对比。模拟结果表明,按照该方法基于0.18μm CMOS工艺设计的工作于1.58 GHz的低噪声放大器,在仅消耗1.9 mA电流的条件下,噪声指数小于1 dB。