基于流水线ADC的高速数据采集系统设计

由于流水线模数转换器（ADC）能在较低的功耗条件下实现中、高精度高速数据采样功能,因而被广泛应用于雷达、通信、医学成像、精确控制等技术领域的数据采集系统。文章介绍了流水线ADC的基本原理及其最新研究成果,并且基于流水线ADC完成了一种14位精度125Msps高速数据采集系统的设计。测试结果表明,该系统在75Msps采样...     

流水线ADC低功耗结构研究

介绍了一种50 MHz,10位,5V流水线模数转换器的设计.为实现低功耗设计目标,将比较器和OTA作为主要优化对象,采用改进的动态比较结构和套筒式余量放大器(OTA)分别实现上述功能.本设计在0.5μm CMOS工艺下实现,工作在50 MHz条件下功耗为190 mW.     

抗辐射低功耗流水线型8位100 MS/s ADC

设计并实现了一种抗辐射低功耗流水线型8位ADC。对流水线型结构的分辨率影响进行分析,确定了最优的级间分辨率和流水线结构。采用多种电路的结构设计,降低了电路功耗。为达到抗辐射指标,对电路进行了抗辐射加固设计。测试结果表明,在3 V电源电压、100 MHz时钟输入频率、70.1 MHz模拟输入频率的条件下,该ADC的SFDR为59.6 dBc,稳态总剂量能力为 2 500 Gy(Si),单粒子闩锁阈值为75 MeV·cm²/mg,功耗为69 mW。该ADC采用0.35 μm CMOS工艺制作,面积为0.75 mm²。该ADC适用于空间环境的通信系统。     

一种用于流水线ADC的高速电压比较器

文章介绍了一种高速电压差分比较器电路，该电路采用了两级运放结构。由前置预放大级和带复位端的闩锁输出级组成。该电路采用0．18μm工艺实现，对其进行了电路原理分析和HSHCE仿真。得到的仿真结果和波形说明该比较器具有速度快、精度高、功耗低的特点，适用于流水线结构的高速模数转换器。     

一种适用于高速高精度流水线ADC的放大器

本文提出了一种新颖的放大器结构.它由两部分组成:前面为跨导放大器,后面则是由电阻反馈形成的跨阻放大器,两种放大器的组合构成了具有高输入阻抗、低输出阻抗的电压放大器.与普通放大器不同的是,在我们设计的工作条件下,它输出端的极点几乎不受负载电容的影响.用该放大器作为预放大级,驱动一单级主放大器所构成的两级运放在负载电容为4pf的情况下实现了超过1GHz的增益带宽积,瞬态分析的结果表明它可以在10ns内达到0.01%的精度(闭环增益为8),而功耗仅有25mW,远低于同性能其他结构的放大器,非常适合作为高速高精度流水线模数转换器中的首级余量放大器使用.     

用于流水线ADC中的带隙基准的研究

传统的BGR(band gap reference circuit)的输出电压等于二极管的导通电压VBE和△VBE之和,输出电压Vref等于1.25V,这种结构限制了适用于低电压低功耗应用.文章介绍了一种新型的CMOS带隙基准源的基本原理--基于电流模式带隙基准源(Current Mode BGR),这种电压源可以使输出电压ref正比于两个电流之和.这两个电流分别正比于VBE和△VBE,通过调整电阻比值,理论上可以得0～VDD的之间的任何值.本电路在smic 0.18μm工艺下实现,为高精度的ADC提供一个精准的参考电压.     

0.25 μm CMOS工艺10位100MHz流水线型ADC设计

采用流水线结构完成了一个10位精度100MHz采样频率的模数转换器的设计.该模数转换器采用采样保持电路、8级1.5位和最后一级2位子模数转换器的结构,电路使用全差分和开关电容电路技术.芯片采用台积电(TSMC)0.25 μm CMOS工艺,电路典型工作电压为2.5V,在室温下,输入信号为5MHz,采样频率100MHz时信号噪声失真比为59.7dB.     

用于高速流水线ADC的低抖动多相时钟产生电路

设计了一种用于高速流水线ADC的多相时钟产生电路。通过采用一种高灵敏度差分时钟输入结构和时钟接收电路,降低了输入时钟的抖动。该多相时钟产生电路已成功应用于一种12位250MSPS流水线ADC,电路采用0.18μm 1P5M 1.8 V CMOS工艺实现,面积为2.5 mm2。测试结果表明,该ADC在全速采样条件下对20 MHz输入信号的信噪比(SNR)为69.92 d B,无杂散动态范围(SFDR)为81.17 d B,积分非线性误差(INL)为-0.4~+0.65 LSB,微分非线性误差(DNL)为-0.2~+0.15 LSB,功耗为320 m W。     

一种基于时间交织流水线架构的高速ADC设计

伴随着宽带雷达系统的发展,信号带宽越来越大,从而对模数转换器(ADC)的转换速度要求也越来越高。为满足宽带系统需求,需要ADC能够在数百兆甚至上GHz转换速度下实现较高精度的数据转换,这对ADC芯片设计提出了很高的要求。基于0.18 μm BiCMOS 工艺,设计了一种时间交织流水线架构的超高速ADC,前端采用一个超高速高精度跟踪保持器,转换核心采用四路并行流水线时域交织工作,内部集成多相位时钟控制电路。实测结果表明:该ADC芯片在800 MS/s 速度下性能良好,部分通道最高工作速度可达1.2 GS/s。     

11位高性能流水线ADC关键电路的分析

近些年,ADC作为模拟信号向数字信号过渡转换的桥梁,有着十分重要意义。而且随着当前无线通信技术的迅速发展,高精度、高速的ADC对于进一步提升通信系统性能也发挥着越来越重要作用。一般来讲,11位流水线ADC能同时兼顾精度与速度,因此可以获得广泛应用于推广。本文主要结合流水线ADC工作原理,对11位高性能流水线ADC关键电流进行研究与分析。     

1-V 9-bit pipelined switched-opamp ADC

A 9-bit 1.0-V pipelined analog-to-digital converter has been designed using the switched-opamp technique. The developed low-voltage circuit blocks are a multiplying analog-to-digital converter (MADC), an improved common-mode feedback circuit for a switched opamp, and a fully differential comparator. The input signal for the converter is brought in using a novel passive interface circuit. The prototype chip, implemented in a 0.5-μm CMOS technology, has differential nonlinearity and integral nonlinearity of 0.6 and 0.9 LSB, respectively, and achieves 50.0-dB SNDR at 5-MHz clock rate. As the supply voltage is raised to 1.5 V, the clock frequency can be increased to 14 MHz. The power consumption from a 1.0-V supply is 1.6 mW     

True background calibration technique for pipelined ADC

A digital background calibration technique for a pipelined analogue-to-digital converter (ADC) is presented. The calibration technique involves the use of a slow, but accurate, ADC in conjunction with a least-mean squares (LMS) algorithm to find the parameters, which correct for residue errors such as finite opamp gain error, capacitor ratio mismatch and charge injection error in a nonideal pipeline stage, resulting in a significant improvement in the INL and the DNL of the ADC     

用于流水线ADC的高精度SHA-Less电路

本文提出了一种适用于高速、高精度流水线ADC的无采样保持运算放大器(SHA-less)结构。使用可变电阻带宽修调电路以及MDAC与flash ADC的对称性设计,减少了两种单元电路间的采样误差,通过增加MDAC采样电容复位时钟和独立的flash ADC采样电容技术,消除了采样电容残留电荷引起的踢回噪声。本设计作为14位125-MS/s流水线ADC的前端转换级,基于ASMC 0.35- BiCMOS工艺的仿真和测试结果表明,前端转换级芯片面积1.4?2.9 mm2,使用带宽修调后,125 MHz采样,30.8 MHz输入信号下,SNR从63.8 dB提高到70.6 dB,SFDR从72.5 dB提高到81.3 dB,转换器的动态性能在150 MHz的输入信号频率下无明显下降。     

A charge-pump and comparator based power-efficient pipelined ADC technique

A charge-pump and comparator based technique is presented for power-efficient pipelined analog-to-digital conversion. The technique takes advantage of a passive charge pump to implement the core function of residue voltage amplification and exploits a comparator-controlled charging circuit to buffer the residue voltage to the next stage. Unlike the conventional buffer circuit using source followers, no voltage headroom is sacrificed in this voltage buffering scheme. The comparator overshoot due to comparator delay is minimized by a self-cancellation scheme. The proposed pipelined ADC technique uses only capacitors, comparators and current sources with digital calibration to achieve low power consumption. Designed and fabricated in a 0.18 μm CMOS technology, a proof-of-concept ADC has measured 39.1 dB SNDR (6.2-bit ENOB) at 25 MS/s while consuming 3.5 mW from a 1.8 V supply.     

Digital background calibration of charge pump based pipelined ADC

In the presented work, digital background calibration of a charge pump based pipelined ADC is presented. A 10-bit 100 MS/s pipelined ADC is designed using TSMC 0.18 µm CMOS technology operating on a 1.8 V power supply voltage. A power efficient opamp-less charge pump based technique is chosen to achieve the desired stage voltage gain of 2 and digital background calibration is used to calibrate the inter-stage gain error. After calibration, the ADC achieves an SNDR of 66.78 dB and SFDR of 79.3 dB. Also, DNL improves to +0.6/–0.4 LSB and INL improves from +9.3/–9.6 LSB to within ±0.5 LSB, consuming 16.53 mW of power.     

11位高性能流水线ADC关键电路的分析

近些年,ADC作为模拟信号向数字信号过渡转换的桥梁,有着十分重要意义。而且随着当前无线通信技术的迅速发展,高精度、高速的ADC对于进一步提升通信系统性能也发挥着越来越重要作用。一般来讲,11位流水线ADC能同时兼顾精度与速度,因此可以获得广泛应用于推广。本文主要结合流水线ADC工作原理,对11位高性能流水线ADC关键电流进行研究与分析。     

A dual-residue pipelined SAR ADC using only zero-crossing signals

This paper presents a dual-residue pipelined successive approximation register (SAR) A/D converter (ADC) that relaxes the accuracy requirement for residue amplifications and thus enables use of only zero-crossing (ZX) signals for the benefits of power efficiency and technology scalability. The dual-residue architecture is illustrated with design of an 11b two-step pipelined ADC consisting of 8b coarse and 5b fine (with 2b over-range) SAR sub-ADCs, which resolve 2b and 1b per SAR conversion cycle, respectively. Two ZX signals (or dual-residues) in opposite polarities automatically available in each 2b SAR cycle are sampled and held at the end of the coarse conversion for use as the full-scale reference for the fine SAR that quantizes a fixed input of zero. Simulations show that the ADC in 45 nm CMOS using typical open-loop circuits for inter-stage residue operation can achieve ENOB?>?10 at 400 MS/s and Schreier FoM?=?171.4 dB without residue gain calibration.

     

A fast foreground digital calibration technique for pipelined ADC

Digital calibration techniques are widely developed to cancel the non-idealities of the pipelined Analog-to-Digital Converters (ADCs). This letter presents a fast foreground digital calibration technique based on the analysis of error sources which influence the resolution of pipelined ADCs. This method estimates the gain error of the ADC prototype quickly and calibrates the ADC simultaneously in the operation time. Finally, a 10 bit, 100 Ms/s pipelined ADC is implemented and calibrated. The simulation results show that the digital calibration technique has its efficiency with fewer operation cycles.