一种全CMOS工艺吉比特以太网串并-并串转换电路

本文介绍了一种单片集成的吉比特以太网串并－并串转换电路。在芯片中，模拟锁相环产生1．25GHz高速时钟（当芯片用于光纤网络，时钟速率就为1．06GHz)，同时一个10到1多路选择器完成并行数据到串行的转换。在接收端，差分输入信号依次经过均衡电路、双端－单端转换电路转换成数字信号。同时，数据和时钟提取电路提取出时钟，并将数据重新同步。最后，串并转换电路完成串行－并行转换和字节同步。实验芯片采用0．35μmSPTM CMOS工艺，芯片面积为1．92mm^2，在最高输入输出数据波特率条件下的功耗为900mW。     

1.25 Gbps并串转换CMOS集成电路

分析了由超高速易重用单元构造的树型和串行组合结构 ,实现了在输入半速率时钟条件下 1 0路到1路吉比特率并串转换。通过理论推导着重讨论了器件延时和时钟畸变对并串转换的影响 ,指出了解决途径。芯片基于 0 .3 5μm CMOS工艺 ,采用全定制设计 ,芯片面积为 2 4.1 9mm2 。串行数据输出的最高工作速率达到 1 .62 Gbps,可满足不同吉比特率通信系统的要求。在 1 .2 5 Gbps标准速率 ,工作电压 3 .3 V,负载为 5 0 Ω的条件下 ,功耗为 1 74.84m W,输出电压峰 -峰值可达到 2 .42 V,占空比为 49% ,抖动为 3 5 ps rms。测试结果和模拟结果一致 ,表明所设计的电路结构在性能、速度、功耗和面积优化方面的先进性。文中设计的芯片具有广泛应用和产业化前景。     

一种用于千兆以太网发接器的高速串-并转换电路

高速串—并转换电路是数字基带传输系统中的重要单元。在对几种常见串—并转换电路的结构和性能进行比较的基础上，利用动态D触发器实现了一种简单实用的结构，并用它设计了适用于十兆以太网发接器的串—并转换电路。同时，对电路中可能存在的问题，如时钟信号的分布，以及动态单元的电荷泄漏，进行了讨论。     

1.25Gbps串并并串转换接收器的低抖动设计

对1.25Gbps应用于千兆以太网的低抖动串并并串转换接收器进行了设计,应用了带有频率辅助的双环时钟数据恢复电路,FLL扩大了时钟数据恢复电路的捕捉范围。基于三态结构的鉴频鉴相从1.25Gbps非归零数据流中提取时钟信息,驱动一个三级的电流注入环形振荡器产生1.25GHz的低抖动时钟。从低抖动考虑引入了均衡器。该串并并串转换接收器采用TSMC0.35μm2P3M3.3V/5V混合信号CMOS技术工艺。测试结果表明了输出并行数据有较好的低抖动性能:1σ随机抖动(RJ)为7.3ps,全部抖动(TJ)为58mUI。     

4 Gbps低功耗并串转换CMOS集成电路

为满足传输数据的高速低功耗的要求,文章设计了一种半速率时钟驱动的二级多路选择开关式的10：1并串转换器。第一级为两个5：1的并行串化器,共用一个多相发生器。多相发生器由五个动态D触发器构成。第二级为一个2：1的并行串化器。采用半速率时钟、多路选择开关结构降低了大部分电路的工作频率,降低了工艺要求,也降低了功耗。通过调整时钟与数据间的相位关系,提高相位裕度,降低了数据抖动。采用1．8V 0．18μm CMOS工艺进行设计。用Hspice仿真器在各种PVT情况下做了仿真,结果表明该转换器在输出4Gbps数据时平均功耗为395μW,抖动18s^-1．     

一种高速并串转换控制电路设计

串行接口常用于高速数据传输,实现多路低速并行数据合成一路高速串行数据.设计了一种高速并串转换控制电路,实现在低频时钟控制下,通过内部锁相环(PLL)实现时钟倍频和数据选通信号,最终形成高速串行数据流,实现每5路全并行数据可按照顺序打包并转换为1路高速串行编码,最后通过一个低电压差分信号(LVDS)接口电路输出.该芯片通过0.18 μmCMOS工艺流片并测试验证,测试结果表明在120 MHz外部时钟频率下,该并串转换控制芯片能够实现输出速度600 Mbit/s的高速串行数据,输出抖动特性约为80 ps,整体功耗约为23 mW.     

一种超高速并串转换电路的新实现方式

在超高速并串转换接口电路设计应用中,提出了一种新的双路恒流结构方式。通过对传统触发器寄存结构和双路恒流结构进行对比,结合电路产品(16位4 G并串转换集成电路),说明了采用新结构方式———双路恒流结构———进行超高速、低功耗并串转换电路设计,在提高电路工作速度、降低功耗方面所取得的成功和优点。     

基于65nm CMOS工艺的高速串并转换电路设计

本文介绍了一种适用于高速差分数据接收的CMOS串并转换电路,该电路主要由时钟电路、1：2数据分割电路和1：5分接器组成。采用65nm工艺,仿真结果表明,在数据传输速度为5Gb/s时功耗为12mW。     

树型结构串并转换电路的设计

采用DEMUX(多路分配器)分级解串、递减降速的树型结构,使电路获得较高转换速度,其优点是在时钟的上升和下降沿采样,充分利用了时钟周期。基于CMOS互补逻辑的电路结构降低了功耗,全定制的设计方法优化了电路性能和版图面积,提高了设计可靠性。本设计采用了华润上华0.6μm CMOS工艺。     

采用自适应连续时间线性均衡器和判决反馈均衡器算法的一种16 Gbit/s 并转串/串转并接口

该文在体硅CMOS工艺下设计了一种16 Gbit/s并转串/串转并接口(SerDes)芯片,该SerDes由4个通道(lanes)和2个锁相环(PLLs)组成。在接收器模拟前端(AFE)采用负阻抗结构连续时间线性均衡器(CTLE),得到22.9 dB高频增益,利用5-tap判决反馈均衡器(DFE)进一步对信号码间干扰(ISI)做补偿,其中tap1做展开预计算处理,得到充足的时序约束条件。采用最小均方根(LMS)算法自适应控制CTLE和DFE的补偿系数来对抗工艺、电源和温度波动带来的影响。测试结果表明,芯片工作在16 Gbit/s时,总功耗为615 mW。发射器输出信号眼高为143 mV,眼宽43.8 ps(0.7UI),接收器抖动容忍指标在各频点均满足PCIe4.0协议要求,工作温度覆盖–55°C～125°C,电源电压覆盖0.9 V±10%,误码率小于1E-12。     

千兆以太网卡芯片A/D转换电路的设计与实现

介绍了一种用于千兆以太网卡芯片的8位125 MS/s CMOS流水线A/D转换电路的设计,包括体系结构设计、电路设计与仿真、版图设计。该A/D转换电路经过TSMC 0.13μm 1P8MCMOS工艺验证,工作电压为1.5 V/2.7 V。芯片测试结果表明,设计的A/D转换电路能够满足千兆以太网卡芯片的性能要求。     

1-Gb/s zero-pole cancellation CMOS transimpedance amplifier for Gigabit Ethernet applications

A zero-pole cancellation transimpedance amplifier (TIA) has been realized in 0.35 μm RF CMOS tech nology for Gigabit Ethernet applications. The TIA exploits a zero-pole cancellation configuration to isolate the input parasitic capacitance including photodiode capacitance from bandwidth deterioration. Simulation results show that the proposed TIA has a bandwidth of 1.9 GHz and a transimpedance gain of 65 dB·Ω for 1.5 pF photodiode capaci tance, with a gain-bandwidth product of 3.4 THz·Ω. Even with 2 pF photodiode capacitance, the bandwidth exhibits a decline of only 300 MHz, confirming the mechanism of the zero-pole cancellation configuration. The input resis tance is 50 Ω, and the average input noise current spectral density is 9.7 pA/(Hz)~(1/2). Testing results shows that the eye diagram at 1 Gb/s is wide open. The chip dissipates 17 mW under a single 3.3 V supply.     

应用于千兆以太网的1-Gb/s 零极点对消CMOS跨阻放大器

A zero-pole cancellation transimpedance amplifier（TIA）has been realized in 0.35μm RF CMOS technology for Gigabit Ethernet applications.The TIA exploits a zero-pole cancellation configuration to isolate the input parasitic capacitance including photodiode capacitance from bandwidth deterioration.Simulation results show that the proposed TIA has a bandwidth of 1.9 GHz and a transimpedance gain of 65 dB·Ωfor 1.5 pF photodiode capaci- tance,with a gain-bandwidth product of 3.4 THz·Ω.Even with 2 pF photodiode capacitance,the bandwidth exhibits a decline of only 300 MHz,confirming the mechanism of the zero-pole cancellation configuration.The input resis- tance is 50Ω,and the average input noise current spectral density is 9.7 pA/√ Hz.Testing results shows that the eye diagram at 1 Gb/s is wide open.The chip dissipates 17 mW under a single 3.3 V supply.     

A 1-GHz, multibit, continuous-time, delta-sigma ADC for Gigabit Ethernet

In this work the design of a continuous-time ΔΣ modulator for Gigabit Ethernet applications is presented. The input bandwidth and oversampling ratio are, respectively, 62.5 MHz and 8, resulting in a clock frequency of 1 GHz. It was designed and implemented in a standard 90 nm CMOS technology. The active area of the modulator measures . It consists of a loop filter based on RC-opamp integrators and a 3-bit quantizer which includes a data weighted averaging scrambler. A digital tuning scheme to deal with process variations has also been included. System level simulations including several non-ideal effects have been carried out in order to determine in detail the performance of the converter. Experimental results show a resolution of 7.1 effective bits, and a power consumption of 10.8 mW from a nominal power supply of 1 V.     

1.8 V千兆以太网接收器模拟前端预均衡电路

介绍了一种用于1.8 V电源电压下的千兆以太网接收器的模拟前端预均衡电路。电路分为三个部分:预处理电路、基带漂移补偿电路和可变增益放大电路,主要实现回波消除、基带漂移补偿和电路增益自动控制等功能。为了与百兆模式兼容,提出了一种预处理电路。仿真结果表明,该电路可以很好地实现回波消除的功能,能够对由于基带漂移引起的信号失真给以补偿,可以提供16级不同的增益,并进行频率补偿。电路采用0.18μm标准CMOS工艺实现。     

A 1.25 Gbps DC-coupled laser diode driver with VBE compensation technique

A 1.25 Gbps integrated laser diode driver (LDD) driving an edge-emitting laser has been designed and fabricated in 0.35 μm BiCMOS technology. The IC can provide independent bias current (5-100 mA) with automatic power control, and modulation current (4-85 mA) with temperature compensation adjustments to minimize the variation in extinction ratio. This paper proposed an unique modulation output driver configuration which is capable of DC-coupling a laser to the driver at +3.3 V supply voltage; and combined a V_BE compensation circuit, the IC can operate at a wide temperature range (−40 to 85 °C) for date rates up to 1.25 Gbps. V_BE compensation technique is used to compensate for variation in V_BE over the operating temperature range so as to minimize the variations in rise and fall time of modulation output over temperatures.     

Dispersion compensation optical fiber modules for 40 Gbps WDM communication systems

Dispersion compensation was originally proposed to equalize pulse distortion.With the development of wavelength division multiplexing (WDM) techniques for large capacity optical communication systems,dispersion compensation technologies have been applied into the field.Fiber-based dispersion compensation is an attractive technology for upgrading WDM communication systems because of its dispersion characteristics and good compatibility with transmission optical fibers.Dispersion compensation fibers and the modules are promising technologies,so they have been receiving more and more attention in recent years.In this work,high performance dispersion compensation fiber modules (DCFMs) were developed and applied for the 40 Giga bit-rate systems.First,the design optimization of the dispersion optical fibers was carried out.In theory,the better the refractive index profile is,the larger the negative dispersion we could obtain and the higher the figure of merit (FOM) for the dispersion optical fiber is.Then we manufactured the fiber by using the plasma chemical vapor deposition (PCVD) process of independent intellectual property rights,and a high performance dispersion optical fiber was fabricated.Dispersion compensation fiber modules are made with the dispersion compensating fibers (DCFs) and pigtail fibers at both ends of the DCFs to connect with the transmission fibers.The DCFMs present the following superior characteristics:low insertion loss (IL),low polarization mode dispersion,good matched dispersion for transmission fibers,low nonlinearity,and good stability for environmental variation.The DCFMs have the functions of dispersion compensation and slope compensation in the wavelength range of 1525 to 1625nm.The experiments showed that the dispersion compensation modules (DCMs) met the requirements of the GR-1221-CORE,GR-2854-CORE,and GR-63-CORE standards.The residual dispersions of the G.652 transmission lines compensated for by the DCM in the C-band are less than 3.0ps/nm,and the dispersion slopes are also compensated for by 100%.With the DCFMs,the 8×80km unidirectional transmission experiments in the 48-channel 40Gbps WDM communication system was successfully made,and the results showed that the channel cost was smaller than 1.20dB,without any bit error.     

Performance evaluation of a buffer-based CSMA/CD protocol for single channel optical Ethernet LAN

Using CSMA/CD, Ethernet suffers capture effect that makes it unsuitable for supporting real-time multimedia traffic. It does not guarantee delay bound and behaves poorly under heavy load conditions, leading to excessive delay, throughput degradation and packet loss because of excessive collisions. Aim of this paper is to increase throughput and reduce average packet transfer delay of CSMA/CD-based LAN by reducing collisions and eliminating packet loss. Here, each user has a finite buffer capacity that helps to reduce collisions and Ethernet capture effect. At the same time, to eliminate packet loss, a new special-jamming signal is used. The network performance in terms of throughput, average packet transfer delay and percentage of collision based on the proposed protocol shows significant improvements. Throughput is increased more than 10% whereas average packet transfer delay and percentage of collision are reduced to less than 1.5 ms and 3%, respectively, compared to conventional protocol.     

塑料光纤在楼宇布线中的应用

塑料光纤（POF）技术日益成熟,其产品在通信领域的应用量不断扩大.文章简述了POF的性能,探讨了各种POF在楼宇布线中应用的可行性,总结了当前楼宇布线标准和POF标准的发展概况,最后分析了当前布线标准所存在的缺陷和POF标准制定的紧迫性.