A simple deductive proof of a stability test for two-dimensional digital filters

A simple proof based on a continuity argument is proposed for a theorem on the stability tests of two-dimensional (2-D) digital filters, independently proposed by Strintzis and by DeCarlo, Murray, and Saeks.     

A primer for digital television RF facility design and construction

With the release of the FCC's (Federal Communications Commission) Sixth Further Notice of Proposed Rulemaking, many television broadcasters are concerned about the design and reconstruction considerations for digital television (DTV). This paper discusses some of these considerations and reviews some of the basic design criteria for a digital television transmission system     

A gallium-arsenide digital phase shifter for clock and controlsignal distribution in high-speed digital systems

The design, implementation, testing, and applications of a gallium-arsenide digital phase shifter and fan-out buffer are described. The integrated circuit provides a method for adjusting the phase of high-speed clock and control signals in digital systems, without the need for pruning cables, multiplexing between cables of different lengths, delay lines, or similar techniques. The phase of signals distributed with the described chip can be dynamically adjusted in eight different steps of approximately 60 ps per step. The IC also serves as a fan-out buffer and provides 12 in-phase outputs. The chip is useful for distributing high-speed clock and control signals in synchronous digital systems, especially if components are distributed over a large physical area or if there is a large number of components     

Exact and Approximate Construction of Digital Phase Modulations by Superposition of Amplitude Modulated Pulses (AMP)

Minimum shift keying and offset QPSK are two well-known modulations which can be interpreted as a set of time/phase-shifted AM pulses. We show in this paper that any constant amplitude binary phase modulation can also be expressed as a sum of a finite number of time limited amplitude modulated pulses (AMP decomposition). New methods for computing autocorrelation and power frequency spectrum are derived, which give very simple results for half-integer index modulations. We also show that the signal can be built with good accuracy using only one optimized pulse ("main pulse"). This synthesis is particularly satisfactory for modulations that have good spectral characteristics and/ or low index.     

用于光学相位检测的数字信号处理系统

介绍了一种利用数字信号处理技术和虚拟仪器技术实现对微弱光学相位信号进行高精度频率、幅度测量的方法。该方法实现了反馈式数据采样率的设定、自适应数字带通带阻滤波器和全数字相敏检波等功能,并且可以对信号相位和强度以及谐波进行精确测量     

数字图书馆本体的构建方法研究与应用

设计并实现了中文领域术语抽取系统,提出了基于前后缀的中文领域术语抽取算法,该算法独立于具体的领域,并且对包含常用前后缀的领域术语具有较好的抽取效果;通过对领域本体构建中关键技术的研究,提出了适用于不同领域的领域本体半自动构建方法;最后,数字图书馆气候变化领域本体的成功构建验证了基于多源数据的领域本体半自动构建方法的有效性,并且该方法可以很方便地移植到其他领域。     

Exact and approximate Fourier rebinning algorithms for the solution of the data truncation problem in 3-D PET

This paper presents an extended 3-D exact rebinning formula in the Fourier space that leads to an iterative reprojection algorithm (iterative FOREPROJ), which enables the estimation of unmeasured oblique projection data on the basis of the whole set of measured data. In first approximation, this analytical formula also leads to an extended Fourier rebinning equation that is the basis for an approximate reprojection algorithm (extended FORE). These algorithms were evaluated on numerically simulated 3-D positron emission tomography (PET) data for the solution of the truncation problem, i.e., the estimation of the missing portions in the oblique projection data, before the application of algorithms that require complete projection data such as some rebinning methods (FOREX) or 3-D reconstruction algorithms (3DRP or direct Fourier methods). By taking advantage of all the 3-D data statistics, the iterative FOREPROJ reprojection provides a reliable alternative to the classical FOREPROJ method, which only exploits the low-statistics nonoblique data. It significantly improves the quality of the external reconstructed slices without loss of spatial resolution. As for the approximate extended FORE algorithm, it clearly exhibits limitations due to axial interpolations, but will require clinical studies with more realistic measured data in order to decide on its pertinence.     

A new approximate solution for scattering by thin dielectric disks of arbitrary size and shape

In this paper, an approximate solution for electromagnetic scattering by a very thin planar homogeneous dielectric object is presented. This solution is obtained from a volumetric integral equation using Fourier transform and is shown to be uniformly valid from low to high frequencies at all incidence angles including edge-on incidence. Validity of the solution is demonstrated through a comparison with canonical objects such as an infinite dielectric slab, and a number of two-dimensional (2-D) and three-dimensional (3-D) dielectric scatterers. For 2-D, and 3-D scatterers, the approximate solution is compared with a method of moments solution. In all cases examined the approximate formulation provides very accurate results except for situations where the dielectric constant is very high.     

A "flying-adder" architecture of frequency and phase synthesis with scalability

Most of today's digital designs, from small-scale digital block designs to system-on-chip (SoC) designs, are based on "synchronous" design principle. Clock is the most important issue in these designs. Frequency and phase synthesis is closely related to the clock generation. A frequency and phase synthesis technique based on phase-locked loop is proposed in that delivers high performance, easy integration, and high stability. However, there are problems associated with this architecture, such as: 1) its highest deliverable frequency is limited by the speed of the accumulator and 2) the phase synthesis circuitry will not work well in certain ranges (dead zone) and in certain conditions (dual stability). This paper presents an improved architecture that addresses these problems. The new frequency synthesis circuitry has scalability for higher output frequency. It also has an internal node whose frequency is twice that of output signal. When duty cycle is not a concern, this signal can be used directly as clock source. The new phase synthesis circuitry is free of "dead zone" and "dual stability." The improved architecture has better performance, is simpler to implement, and is easier to understand.     

变压器防震抗干扰的新工艺

本文叙述了C型双线包全波整流用变压器引起机震、干扰大的根源,提出了消除震动、减少干扰的制作新工艺。     

A universal digital platform for the construction of self-organizing wireless sensor networks for industrial safety and ecological monitoring systems

The design results of a universal digital platform intended for the construction of self-organizing wireless sensor networks of industrial safety and ecological monitoring systems are given. The design-manufacturing principles for the creation of miniature wireless sensor assemblies (WSAs), ensuring the integration of gas sensors of different types, their self-contained power supply, self-deployment of the sensor network, and design features of the miniature WSAs based on a specialized receiving–transmitting module, constructed in accordance with the up-to-date 2.5D assembly technique using a silicon substrate, are considered. The basic principle of the operation of highly sensitive WSA elements, which are intended for the determination of toxic and explosive gases, and the basic development principles of a smart power source integrated into the sensor assembly housing, which ensures its uninterrupted operation for a long time through the electric energy generation and accumulation units from alternative energy supply sources, are presented. Problems related to the development and remote automatic renovation of the WSA software, architecture of the server software for data acquisition, and analysis of industrial and ecological monitoring problems are considered.     

A new procedure for the design of high order minimum phase FIR digital or CCD filters

The approximation problem for high-order minimum phase FIR filter is solved without requiring any polynomial factorization. A modified Parks-McClellan program is used to compute the amplitude function; the minimum phase function is then derived by a method using the FFT algorithm. The procedure is illustrated by the design of various high order filters; short computation time with no numerical troubles is achieved.     

Design and performance of "1.25-µm" CMOS for digital applications

This paper presents a detailed approach for the design and performance analysis of 1.25-µm CMOS digital circuit technology based on relatively simple sets of fundamental device parametric and circuit equations. As a start, a topological and "in-depth" baseline is assumed for this 1.25-µm CMOS technology, based, in part, on a set of achievable lithographic feature sizes and alignment tolerances together with a set of reasonable process geometric parameters. The process baseline is TWIN-WELL CMOS using n^-epi on an n⁺substrate as the host starting material. Two of the key geometric parameters defined are effective channel length, Le= 1 µm, and gate oxide thickness, tox= 250 Å. Other dimensions have been selected using quasi-scaling rules consistent with a 2λ of 1.25 µm. The design process starts with the selection of the average "well" doping levels from a consideration of some key short-channel effects: simple charge sharing and drain-induced barrier lowering (DIBL). The selection of a suitable operating voltage, VDD, is considered during this process as it effects junction breakdown voltage, gate oxide fields, and more importantly, potential hot-electron injection. Additional process design analyses are presented with respect to the establishment of gate threshold voltages and field inversion voltages. A simple transient analysis procedure is developed for a basic inverter structure which yields results close to those obtained through more detailed SPICE simulations. A unit delay (single fan-out) analysis is performed yielding delays of 214 ps for a VDDof 5 V and 270 ps for a VDDof 3.3 V.     

数模混合电路中的"地跳动"问题研究

针对数模混合电路中接地问题进行研究。从集成芯片的角度讨论了“地跳动”问题的根源，然后运用得到的结论对一般的数模混合电路进行分析，提出解决的方案，使数字噪声对模拟电路的干扰降到最低。     

S.A.W. implementation of whitening filters for satellite digital communications

The ability of a s.a.w. filter to match arbitrary frequency response is demonstrated for an x/sin x specification. This yields a valuable improvement for satellite digital communications around the 70 MHz intermediate frequency. Both design rules and experimental results are reported.     

A low-complexity joint color demosaicking and zooming algorithm for digital camera.

This paper presents a low complexity joint color demosaicking and digital zooming algorithm for single-sensor digital cameras. The proposed algorithm directly extracts edge information from raw sensor data for interpolation in both demosaicking and zooming to preserve edge features in its output. This allows the extracted information to be exploited consistently in both stages and also efficiently, as no separate extraction process is required in different stages. The proposed algorithm can produce a zoomed full-color image as well as a zoomed Bayer color filter array image with outstanding performance as compared with conventional approaches which generally combine separate color demosaicking and digital zooming schemes.     

基于V/F变换下的数字相敏检测监控光学膜厚

本文采用基于电压-频率变换(V/F)的数字相敏检测技术应用于光学监控信号检测,得到的被检测信号的幅度,即光学监控信号波形.而且针对光学监控系统中被检测信号特点,从理论分析角度说明了本方案抑制被检测信号低次谐波和白噪声的性能.仿真分析中针对加入了2,3,4次谐波和零均值随机白噪声,信噪比为20dB,频率为166Hz的被检测信号,利用本方案检测出光学监控信号反射率最大误差＜0.2%.分别利用本方案检测出的光学监控信号和理想监控信号读取反射率极值点对应薄膜厚度,对比可知采用本方案监控膜厚理论误差＜2nm.     

On feasibility of a multiplier-less phase-shifting scheme for digital phase modulation and its VLSI implementation

In this paper, a multiplier-less phase-shifting scheme for digital phase modulation is proposed and its implemantation for very large-scale integration (VLSI) is examined. The abrupt phase shift of carrier waveform, required after each data transition in digital phase-modulation scheme, is realized by incrementing the frequency of a voltage-controlled oscillator (VCO) for a short duration, immediately following the data transition. The momentary increase in VCO frequency is realized by feeding the VCO with narrow control pulses, derived from the baseband data stream using a simple supporting circuit. This work currently deals with the VLSI design for binary phase-shift keying (BPSK). However, the underlying concept is generic and hence capable of implementing other digital phase-modulation schemes, such as, quadrature PSK (QPSK), quadrature amplitude modulation (QAM) etc, with a programmable control circuit for the VCO. Thus, the proposed multiplier-less phase-shifting scheme can find useful application in broadband wireless networks employing adaptive modulation schemes.