负载型复合载体及其镍基催化剂的性能

采用溶胶-凝胶法制备了负载型ZrO_2/Al_2O_3和ZrO_2/Al_2O_3-SiO_2复合载体,研究了不同复合载体对Ni基催化剂CO_2重整甲烷反应和性能的影响,并用XRD、IR、TPR、TPD和BET等方法对复合载体及催化剂进行了表征。结果表明,ZrO_2负载在基载体后比表面积、碱性、活性组分Ni的分散度和Ni与ZrO_2的相互作用增大。NiO在复合载体表面的分散容量与ZrO_2的负载量有关,ZrO_2的负载量为37．5%时NiO的分散容量达最高值(24．0%)。与Ni/ZrO_2相比,Ni/ZrO_2/Al_2O_3-SiO_2和Ni/ZrO_2/Al_2O_3催化剂对CO_2的吸附能力增大,CO_2吸附量增加,酸强度降低,CO_2重整CH_4反应活性提高,其中以Ni/ZrO_2/Al_2O_3催化剂的活性最好。     

基于子空间分解的快速盲均衡解调算法

基于高阶统计的盲均衡算法需要大量的观测数据,当观测数据有限或信道变化较快时,由于模型失配将使均衡性能严重下降,因此短数据、快收敛是近年来盲均衡技术研究的主要方向之一。本文讨论了基于子空间分解的信道识别和盲均衡技术,利用卡尔曼滤波方程,给出了一种快速收敛的盲均衡解调算法,算法只需要较少的数据样本,仿真结果表明该方法是有效的。     

SISAR中运动目标全息信号的表示及仿真研究

在运用阴影逆合成孔径雷达(SISAR)对运动目标进行成像和识别研究中,需要得到相关目标的全息信号。该文在分析目标侧影轮廓与其全息信号关系的基础上,导出了一种更具普遍意义的全息信号的表达形式,式中的各组成具有明确的物理含义。为验证其在实际应用中的有效性,以外场试验获得两种目标的全息信号为比较对象,参照外场试验条件进行了仿真。比较结果说明了该仿真方法实际有效。     

光纤环绕制的实现技术

光纤陀螺的应用对光纤环的绕制提出了更高的要求，为满足工程化的需求，本文就光纤环四级绕法的实现技术和方法进行了研究。     

双正交全反射型光学电流互感器传感头精度分析

本文对双正交全反射法光学电流互感器传感头的精度进行了分析，分析结果表明采用小折射率的磁光材料以及大入射角传感头方案可以降低对加工精度的要求。同时对双正交全反射法和临界角入射法这两种设计方案中加工精度对传感器精度的影响进行了比较，得出了双正交全反射法在加工精度要求方面较临界角入射法宽松的结论。     

利用电光效应实现方位信息传递的理论与误差分析

本文设计了一种利用晶体的线性电光效应获取发射和接收两部分装置间相对转动的方位信息的光学系统，推导了出射的о光和e光的强度差与发射、接收两部分相对转角之间的关系，并对可能出现的误差进行了分析。     

应变SiGe沟道pMOSFET的击穿特性

以半导体器件二维数值模拟程序Medici为工具,模拟和对比了SiGepMOS同SipMOS的漏结击穿电压随栅极偏压、栅氧化层厚度和衬底浓度的变化关系;研究了SiGepMOS垂直层结构参数硅帽层厚度、SiGe层厚度及Ge剂量和p+ δ掺杂对于击穿特性的影响.发现SiGepMOS击穿主要由窄带隙的应变SiGe层决定,击穿电压明显低于SipMOS并随Ge组分增加而降低;SiGe/Si异质结对电场分布产生显著影响,同SipMOS相比电场和碰撞电离具有多峰值分布的特点;Si帽层及SiGe层参数对击穿特性有明显影响,增加p型δ掺杂后SiGepMOS呈现穿通击穿机制     

新型薄膜SOI高压MOSFET的研制

研制了两种薄膜SOI高压MOSFET,一种是一般结构,另一种是新的双漂移区结构.两者的栅宽均为76 0μm,有源区面积为8.5 8×10 - 2 m m2 ,测试表明其击穿电压分别为17V和2 6 V,导通电阻分别为80Ω和6 5Ω.     

A single-V/sub t/ low-leakage gated-ground cache for deep submicron

In this paper, we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high-performance cache memories using single V/sub t/ (transistor threshold voltage) process. We utilize the concept of gated-ground (nMOS transistor inserted between ground line and SRAM cell) to achieve a reduction in leakage energy without significantly affecting performance. Experimental results on gated-ground caches show that data is retained (DRG-Cache) even if the memory is put in the standby mode of operation. Data is restored when the gated-ground transistor is turned on. Turning off the gated-ground transistor in turn gives a large reduction in leakage power. This technique requires no extra circuitry; the row decoder itself can be used to control the gated-ground transistor. The technique is applicable to data and instruction caches as well as different levels of cache hierarchy, such as the L1, L2, or L3 caches. We fabricated a test chip in TSMC 0.25-/spl mu/m technology to show the data retention capability and the cell stability of the DRG-Cache. Our simulation results on 100-nm and 70-nm processes (Berkeley Predictive Technology Model) show 16.5% and 27% reduction in consumed energy in L1 cache and 50% and 47% reduction in L2 cache, respectively, with less than 5% impact on execution time and within 4% increase in area overhead.     

A New Low Voltage CMOS Transconductor for VHF Filtering Applications

In this paper, a new differential input CMOS transconductor circuit for VHF filtering application is introduced. The new circuit has a very high frequency bandwidth, large linear differential mode input range and good common mode signal rejection capability. Using 0.35 m CMOS technology with 3 V power supply, the transconductor has a ±0.9 V linear differential input range with a –54 dB total harmonic distortion (THD) and more than 1 GHz – 3 dB bandwidth. The large signal DC analysis and small signal ac analysis derived by compact equations are in line with SpectreS simulation. A 3rd order elliptic low pass g _m-C filter with a cutoff frequency of 150 MHz is demonstrated as an application of the new transconductor.