2.3–21 GHz broadband and high linearity distributed low noise amplifier

This paper focuses on the design of a 2.3–21 GHz Distributed Low Noise Amplifier (LNA) with low noise figure (NF), high gain (S₂₁), and high linearity (IIP3) for broadband applications. This distributed amplifier (DA) includes S/C/X/Ku/K-band, which makes it very suitable for heterodyne receivers. The proposed DA uses a 0.18 μm GaAs pHEMT process (OMMIC ED02AH) in cascade architecture with lines adaptation and equalization of phase velocity techniques, to absorb their parasitic capacitances into the gate and drain transmission lines in order to achieve wide bandwidth and to enhance gain and linearity. The proposed broadband DA achieved an excellent gain in the flatness of 13.5 ± 0.2 dB, a low noise figure of 3.44 ± 1.12 dB, and a small group delay variation of ±19.721 ps over the range of 2.3–21 GHz. The input and output reflection coefficients S₁₁ and S₂₂ are less than −10 dB. The input compression point (P_1dB) and input third-order intercept point (IIP3) are −1.5 dBm and 11.5 dBm, respectively at 13 GHz. The dissipated power is 282 mW and the core layout size is 2.2 × 0.8 mm².     

基于残差决策的自动飞行控制系统远程实时故障诊断

针对自动飞行控制系统结构复杂、关联部件众多,发生故障时诊断时间长,从而影响飞机运行效率的问题,提出一种基于飞机通信寻址报告系统(ACARS)的远程实时故障诊断方案。首先,分析自动飞行控制系统的故障特点,设计搭建检测滤波器;然后,利用ACARS数据链实时发送的自动飞行控制系统的关键信息进行相关部件的残差计算,并根据残差决策算法进行故障诊断及定位;最后,针对不同故障部件残差间的差异大、决策门限无法统一的缺点,提出基于二次差值的残差决策改进算法,减缓了检测对象的整体变化趋势,降低了随机噪声和干扰的影响,避免了将瞬态故障诊断为系统故障的情况。实验仿真结果表明,基于二次差值的改进残差决策算法避免了多决策门限的复杂性,在采样时间为0.1 s的情况下,故障检测所需时间大约为2 s,故障检测时间大幅降低,有效故障检测率大于90%。     

Rethinking Enterprise Architecture for Sustainable Energy System Development

The development of a sustainable energy system throughout an enterprise is a complex task, which requires an agile holistic approach. Such an approach needs to include a variety of objectives including energy strategy formation and strategic decision-making, which are directly related to the analysis and management of the main areas of sustainable development:The economic, technological, environmental, and social. These multidimensional requirements of sustainability are often difficult to achieve within the enterprise, because these aspects are interrelated and influenced by various internal and external environment factors. This paper first reviews the main challenges for an energy system, and then demonstrates how a strategic agile enterprise architecture driven approach could effectively guide the sustainable energy system development. The study presented in this paper provides a holistic approach that contributes to the advancement and usage of literature dealing with issues of sustainable energy system development and agile enterprise architecture, which has not been discussed before to any great extent.     

Resistive switching characteristics of ZnO–graphene quantum dots and their use as an active component of an organic memory cell with one diode-one resistor architecture

We investigated the resistive switching characteristics of a polystyrene:ZnO–graphene quantum dots system and its potential application in a one diode-one resistor architecture of an organic memory cell. The log–log I–V plot and the temperature-variable I–V measurements revealed that the switching mechanism in a low-current state is closely related to thermally activated transport. The turn-on process was induced by a space-charge-limited current mechanism resulted from the ZnO–graphene quantum dots acting as charge trap sites, and charge transfer through filamentary path. The memory device with a diode presented a ∼10³ I_ON/I_OFF ratio, stable endurance cycles (10² cycles) and retention times (10⁴ s), and uniform cell-to-cell switching. The one diode-one resistor architecture can effectively reduce cross-talk issue and realize a cross bar array as large as ∼3 kbit in the readout margin estimation. Furthermore, a specific word was encoded using the standard ASCII character code.     

Combined hardware–software multi-parallel prefiltering on the Convey HC-1 for fast homology detection

Protein databases used in research are huge and still grow at a fast pace. Many comparisons need to be done when searching similar (homologous) sequences for a given query sequence in these databases. Comparing a query sequence against all sequences of a huge database using the well-known Smith–Waterman algorithm is very time-consuming. Hidden Markov Models pose an opportunity for reducing the number of entries of a database and also enable to find distantly homologous sequences. Fewer entries are achieved by clustering similar sequences in a Hidden Markov Model. Such an approach is used by the bioinformatics tool HHblits. To further reduce the runtime, HHblits uses two-level prefiltering to reduce the number of time-consuming Viterbi comparisons. Still, prefiltering is very time-consuming. Highly parallel architectures and huge bandwidth are required for processing and transferring the massive amounts of data. In this article, we present an approach exploiting the reconfigurable, hybrid computer architecture Convey HC-1 for migrating the most time-consuming part. The Convey HC-1 with four FPGAs and high memory bandwidth of up to 76.8 GB/s serves as the platform of choice. Other bioinformatics applications have already been successfully supported by the HC-1. Limited by FPGA size only, we present a design that calculates four first-level prefiltering scores per FPGA concurrently, i.e. 16 calculations in total. This score calculation for the query profile against database sequences is done by a modified Smith–Waterman scheme that is internally parallelized 128 times in contrast to the original Streaming ‘Single Instruction Multiple Data (SIMD)’ Extensions (SSE)-supported implementation where only 16-fold parallelism can be exploited and where memory bandwidth poses the limiting factor. Preloading the query profile, we are able to transform the memory-bound implementation to a compute- and resource-bound FPGA design. We tightly integrated the FPGA-based coprocessor into the hybrid computing system by employing task-parallelism for the two-level prefiltering. Despite much lower clock rates, the FPGAs outperform SSE-based execution for the calculation of the prefiltering scores by a factor of 7.9.     

Simplified anode architecture for PEMFC systems based on alternative fuel feeding: Experimental characterization and optimization for automotive applications

The need to reduce PEMFC systems cost as well as to increase their durability is crucial for their integration in various applications and especially for transport applications. A new simplified architecture of the anode circuit called Alternating Fuel Feeding (AFF) offers to reduce the development costs. Requiring a new stack concept, it combines the simplicity of Dead-End Anode (DEA) with the operation advantages of the hydrogen recirculation. The three architectures (DEA, recirculation and AFF) are compared in terms of performance on a 5-kW test bench in automotive conditions, through a sensitivity analysis. A gain of 17% on the system efficiency is observed when switching from DEA to AFF. Moreover, similar performances are obtained both for AFF and for recirculation after an accurate optimization of the AFF tuning parameters. Based on DoE data, a gain of 25% on the weight of the anodic line has been identified compared to pulsed ejector architecture and 43% with the classic recirculation architecture with blower only (Miraï).     

一种北斗联合低轨星座的导航增强方法研究

单纯依靠北斗导航系统提供定位导航授时服务,存在卫星信号落地功率低、易受遮蔽和阻断的不足。针对此问题,研究了一种北斗联合低轨星座实现导航增强的系统架构;提出了一种新的适应严重遮蔽或干扰条件下,基于到达时间(TOA)和到达频率(FOA)联合观测的定位解算算法;对高中低轨混合星座条件下的覆盖特性和精度衰减因子进行了仿真分析。分析结果表明,用户可见星数平均增加了64.2%,位置精度衰减因子(PDOP)平均改善了28.7%。研究结果可为下一代北斗的论证设计与研制建设提供参考借鉴。     

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

AD HOC网络管理综述

由于AD HOC网络自身的特点，其网络管理很多方面与固定网络不同，如移动性管理和体系结构管理等。讨论了AD HOC网络管理的各个方面，并列举了各个方面的设计思路和已有的相关算法的简介。