用于电弧检测的电力专用SoC设计

针对传统的电弧电路故障检测结果不准确的问题,设计用于电弧检测的SoC系统,并且在55nm工艺下进行流片验证。采用包含两种结构的模数转换器的片上电压源,设计了锁相环以及复位电路,精度最高可达8.67 bit。验证结果表明,本设计可提高电弧检测的准确性。     

干扰条件下的“北斗”信号解扩重构DOA估计

在干扰条件下，卫星导航抗干扰波束形成算法往往需要卫星信号波达方向（Direction-of-Arrival，DOA）的先验信息。但当存在低信噪比信号或主动干扰源时，常规的DOA估计算法性能急剧下降甚至失效。针对此问题，提出了一种被干扰信号压制的低信噪比“北斗”信号的DOA估计算法。该算法首先通过对接收信号进行子空间投影抑制干扰信号，然后对抑制干扰后的信号进行解扩重构处理，最后通过多重信号分类算法完成对“北斗”信号的DOA估计。仿真结果表明，在干扰信号干信比80 dB条件下，“北斗”信号DOA估计误差在5°以内，为下一步进行波束形成计算提供了高精度的入射角信息。     

基于信号增强的缓慢泄漏检测方法

目前管道泄漏检测方法可有效检测突发泄漏，对于缓慢泄漏则存在检测灵敏度低、定位不准确等问题。基于此，提出了一种基于信号增强的缓慢泄漏检测方法。通过信号压缩（抽取及移位）克服缓慢泄漏压力信号下降平缓的缺点；根据声波信号具有波形尖锐突出、对突发泄漏敏感的优点，通过建立以压力为输入、虚拟声波为输出的声波信号变送器模型，将压力信号转换为声波信号，克服了泄漏压力信号容易被淹没在管道压力波动及背景噪声中的缺点，实现了缓慢泄漏信号的增强；利用临近插值方法重构虚拟声波信号，基于延时互相关分析实现了缓慢泄漏的准确定位。实验结果表明，该方法具有显著的信号增强效果和定位精度，实现了缓慢泄漏的准确检测。     

应用膨胀算法提取目标的直接定位算法

为了解决被动雷达系统中的多发射源定位问题，提出了一种基于多重信号分类(MUSIC)算法和图像膨胀(IE)算法的直接定位方法。该方法结合了谱分析中的MUSIC思想，通过对接收量测协方差矩阵进行特征分析求解目标的位置。首先，在目标个数未知的前提下，利用Akaike信息准则(AIC)来确定模型阶数；然后，推导了基于MUSIC的定位代价函数；之后，利用图像膨胀算法处理得到的代价函数平面；最后，膨胀处理后的输出为目标个数及目标位置的估计值。提出的算法有效地解决了目标检测及提取的问题，能够确定多个目标的位置坐标，为后续的定位性能分析提供可能性，也保证了算法的完整性。进一步地分析了多个临近目标情况下影响目标提取性能的主要因素。     

A Mobile Cloud-Based eHealth Scheme

Mobile cloud computing is an emerging field that is gaining popularity across borders at a rapid pace. Similarly, the field of health informatics is also considered as an extremely important field. This work observes the collaboration between these two fields to solve the traditional problem of extracting Electrocardiogram signals from trace reports and then performing analysis. The developed system has two front ends, the first dedicated for the user to perform the photographing of the trace report. Once the photographing is complete, mobile computing is used to extract the signal. Once the signal is extracted, it is uploaded into the server and further analysis is performed on the signal in the cloud. Once this is done, the second interface, intended for the use of the physician, can download and view the trace from the cloud. The data is securely held using a password-based authentication method. The system presented here is one of the first attempts at delivering the total solution, and after further upgrades, it will be possible to deploy the system in a commercial setting.     

一款紧凑增强型可变阻抗电磁带隙结构

基于传统AI-EBG结构,提出了一种小尺寸的增强型电磁带隙结构,实现了从0.5~9.4 GHz的宽频带-40 dB噪声抑制深度,且下截止频率减少到数百MHz,可有效抑制多层PCB板间地弹噪声。文中同时研究了EBG结构在高速电路应用时的信号完整性问题,使用差分信号方案可改善信号完整性。     

Voltage reference architectures for low-supply-voltage low-power applications

This paper presents a voltage reference generator architecture and two different realizations of it that have been fabricated within a standard 0.18 μm CMOS technology. The architecture takes the advantage of utilizing a sampled-data amplifier (SDA) to optimize the power consumption. The circuits achieve output voltages on the order of 190 mV with temperature coefficients of 43 ppm/°C and 52.5 ppm/°C over the temperature range of 0 to 120°C without any trimming with a 0.8 V single supply. The power consumptions of the circuits are less then 500 nW while occupying an area of 0.2 mm² and 0.08 mm², respectively.     

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

智能型电子式变频电动执行器及其应用

针对原有电动执行器只有以低速运行，通过极强的微调才能修正微小偏差这一缺点，提出智能型电动执行器与各种阀体譬合，利用数字化变频技术，改造目前采用模拟技术的电动执行器，使之具有变速运行、动态响应块，调节定位精度高、稳定性好，故障率低、使用寿命长和应用场合广泛的特点。     

一种改进型自适应加权模糊均值滤波算法

针对原有的自适应加权模糊均值AWFM滤波器对局部噪声幅度估计不足的缺点。提出了一种新的改进型自适应加权模糊均值MAWFM滤波算法。该算法采用了一种新的模糊检测方法，可以同时检测各个像素点的正负向噪声幅度，从而能够建立一种新的自适应的模糊信号空间，以适应噪声在各个图像局部的变化。实验结果表明，MAWFM滤波器比以前的AWFM滤波器及传统的中值滤波器均有较优越的性能。