用于电弧检测的电力专用SoC设计

针对传统的电弧电路故障检测结果不准确的问题,设计用于电弧检测的SoC系统,并且在55nm工艺下进行流片验证。采用包含两种结构的模数转换器的片上电压源,设计了锁相环以及复位电路,精度最高可达8.67 bit。验证结果表明,本设计可提高电弧检测的准确性。     

A Global Maximum Error Controller Based Nonlinearity Aware TPWL Method for Reducing Nonlinear Systems

Abstract

Model order reduction is a common practice to reduce large order systems so that their simulation and control become easy. Nonlinearity aware trajectory piecewise linear is a variation of trajectory piecewise linearization technique of order reduction that is used to reduce nonlinear systems. With this scheme, the reduced approximation of the system is generated by weighted sum of the linearized and reduced sub-models obtained at certain linearization points on the system trajectory. This scheme uses dynamically inspired weight assignment that makes the approximation nonlinearity aware. Just as weight assignment, the process of linearization points selection is also important for generating faithful approximations. This article uses a global maximum error controller based linearization points selection scheme according to which a state is chosen as a linearization point if the error between a current reduced model and the full order nonlinear system reaches a maximum value. A combination that not only selects linearization points based on an error controller but also assigns dynamic inspired weights is shown in this article. The proposed scheme generates approximations with higher accuracies. This is demonstrated by applying the proposed method to some benchmark nonlinear circuits including RC ladder network and inverter chain circuit and comparing the results with the conventional schemes.     

PSO优化多核RVM的模拟电路故障预测

针对模拟电路健康管理的特点，提出了一种基于PSO优化多核RVM的模拟电路故障预测方法。利用参数分析得到电路的输出频域响应作为特征，计算其与电路无故障标准响应的欧氏距离来表征电路元件健康值，将多个核函数线性组合，并用PSO优化多核RVM参数后的模型实现对各个时间点元件的健康值变化轨迹进行预测。仿真结果表明，该方法在小样本情况下，预测效果优于单一核函数的RVM模型，适用于健康管理中实时预测，具有较好的实用性。     

一款紧凑增强型可变阻抗电磁带隙结构

基于传统AI-EBG结构,提出了一种小尺寸的增强型电磁带隙结构,实现了从0.5~9.4 GHz的宽频带-40 dB噪声抑制深度,且下截止频率减少到数百MHz,可有效抑制多层PCB板间地弹噪声。文中同时研究了EBG结构在高速电路应用时的信号完整性问题,使用差分信号方案可改善信号完整性。     

Voltage reference architectures for low-supply-voltage low-power applications

This paper presents a voltage reference generator architecture and two different realizations of it that have been fabricated within a standard 0.18 μm CMOS technology. The architecture takes the advantage of utilizing a sampled-data amplifier (SDA) to optimize the power consumption. The circuits achieve output voltages on the order of 190 mV with temperature coefficients of 43 ppm/°C and 52.5 ppm/°C over the temperature range of 0 to 120°C without any trimming with a 0.8 V single supply. The power consumptions of the circuits are less then 500 nW while occupying an area of 0.2 mm² and 0.08 mm², respectively.     

智能型电子式变频电动执行器及其应用

针对原有电动执行器只有以低速运行，通过极强的微调才能修正微小偏差这一缺点，提出智能型电动执行器与各种阀体譬合，利用数字化变频技术，改造目前采用模拟技术的电动执行器，使之具有变速运行、动态响应块，调节定位精度高、稳定性好，故障率低、使用寿命长和应用场合广泛的特点。     

Implementing Qubits with Superconducting Integrated Circuits

Superconducting qubits are solid state electrical circuits fabricated using techniques borrowed from conventional integrated circuits. They are based on the Josephson tunnel junction, the only non-dissipative, strongly non-linear circuit element available at low temperature. In contrast to microscopic entities such as spins or atoms, they tend to be well coupled to other circuits, which make them appealling from the point of view of readout and gate implementation. Very recently, new designs of superconducting qubits based on multi-junction circuits have solved the problem of isolation from unwanted extrinsic electromagnetic perturbations. We discuss in this review how qubit decoherence is affected by the intrinsic noise of the junction and what can be done to improve it. PACS: 03.67.-a, 03.65.Yz, 85.25.-j, 85.35.Gv     

宽工作电压范围单电源CMOS误差放大器

采用0.8μm标准数字CMOS工艺(VTN0=0.836V,VTP0=0.930V),设计并流片验证了具有宽工作电压范围(3～6V),可作SOC系统动态电源管理芯片内部误差放大器应用的单电源CMOS运算放大器。该误差放大器芯核同时具有适合低电压工作,并对工艺参数变化不敏感的优点。对于相同的负载情况,在3V的工作电压下,开环电压增益AD=83.1dB,单位增益带宽GB=2.4MHz,相位裕量Φ=85.2°,电源抑制比PSRR=154.0dB,转换速率Sr=2.2V/μs;在6V工作电压下,AD=85.1dB,GB=2.4MHz,Φ=85.4°,PSRR=145.3dB,Sr=3.4V/μs。     

Synchronous Full-Scan for Asynchronous Handshake Circuits

Handshake circuits form a special class of asynchronous circuits that has enabled the industrial exploitation of the asynchronous potential such as low power, low electromagnetic emission, and increased cryptographic security. In this paper we present a test solution for handshake circuits that brings synchronous test-quality to asynchronous circuits. We add a synchronous mode of operation to handshake circuits that allows full controllability and observability during test. This technique is demonstrated on some industrial examples and gives over 99% stuck-at fault coverage, using test-pattern generators developed for synchronous circuits. The paper describes how such a full-scan mode can be achieved, including an approach to minimize the number of dummy latches in case latches are used in the data path of the handshake circuit.