基于FPGA的故障修复演化技术研究

演化硬件的自修复特性能够有效解决电路系统的可修复性故障,但演化硬件存在电路演化速度慢、演化成功率不高的缺陷,如何在修复约束期限内完成电路演化成为关键难点。提出一种基于演化硬件的实时系统容错架构,通过建立故障树实时监测电路故障,利用故障补偿机制维持系统正常运行,并采用演化硬件技术修复电路故障,实现故障的在线实时修复。采用FPGA构建容错系统测试环境,通过随机故障注入对比验证不同演化算法的自修复能力,实验结果表明,在实时性约束下故障电路的修复率达到95%,有效提升了系统的稳定性和可靠性。     

基于独立演化系统的演化硬件实验

演化硬件是指能利用进化算法实现自修复和自适应的硬件。融合了电路自动设计、可重构硬件、人工智能和自治系统等相关内容它不仅是一种具有自适应与自修复特性的仿生物态硬件电路,是新兴的仿生电子学的主要研究内吝之一,而且是一种新颖的硬件设计思想与方法。该文设计了一种基于FPTA的DSP独立演化系统,并对外部演化结果进行下载测试,实现了对外部演化结果的检验通过测试证明该演化系统适用于FPTA单细胞或多细胞演化实验。     

基于独立演化系统的演化硬件实验

演化硬件是指能利用进化算法实现自修复和自适应的硬件。融合了电路自动设计、可重构硬件、人工智能和自治系统等相关内容。它不仅是一种具有自适应与自修复特性的仿生物态硬件电路,是新兴的仿生电子学的主要研究内容之一,而且是一种新颖的硬件设计思想与方法。该文设计了一种基于FPTA的DSP独立演化系统,并对外部演化结果进行下载测试,实现了对外部演化结果的检验。通过测试证明该演化系统适用于FPTA单细胞或多细胞演化实验。     

仿生容错系统演化修复能力研究

基于演化硬件技术构建一种仿生容错系统,通过不同模式、数量的故障注入对其演化修复能力进行研究,得到系统故障状况与演化修复能力间的关系：(1)随着故障数量的增加,系统演化修复能力的主要影响因素从演化算法的效率逐步向演化修复过程中的故障“躲避”概率转移;(2)系统的演化修复能力与故障数量符合指数衰减规律。     

基于EHW和RBT的不同类型故障快速修复策略

由于常规的基于EHW的故障自修复策略存在故障修复类型单一、面对大规模电路修复速度慢、不能实时快速自适应的修复故障等问题,在前期工作中提出了基于EHW和RBT的故障自修复策略。基于此,本文对不同故障类型下的故障快速修复策略进行了研究。由于不可能预知实时检测到的故障类型,在本文的自适应修复策略中,统一将检测到的故障作为固定型故障进行修复。演化算法根据故障信息演化矫正电路,MUX根据实时检测到的故障信息进行开断,从而保证UUT的正常运行。通过实例仿真证明,本文提出的快速修复策略的可行性和有效性得到了验证。     

基于动态可重构FPGA的自演化硬件概述

演化硬件研究如何利用遗传算法进行硬件自动设计,或者设计随外界环境变化而自适应地改变自身结构的硬件,在电子设计自动化、自主移动机器人控制器、无线传感器网络节点等领域都有潜在的应用价值. 自演化硬件是在硬件内部完成遗传操作和适应度计算,利用支持动态部分可重构的FPGA芯片上的微处理器核实现遗传算法,模拟生物群体演化过程搜索可能的电路设计并配置片上的可重构逻辑,找到最优或较优的设计结果,从而实现自适应硬件. 当电路发生故障时,自演化硬件自动搜索新的配置,利用片上冗余资源取代故障区域,从而实现自修复硬件. 介绍了基于动态部分可重构FPGA的自演化硬件的基本思想、体系结构以及研究现状,总结并提出了亟待解决的关键技术,指出高效的电路染色体编码表示与可重构逻辑配置位串之间的映射方式是当前研究的重点之一.     

基于演化硬件的电路自重构修复方法

演化硬件是当前解决系统设计复杂度和系统可靠性这一矛盾最有潜力的技术.它是通过融入演化机制来实现电子系统的实时自重构,并具备了自组织、自适应和自修复的特性,这为硬件容错技术开辟了一条崭新的途径.目前演化硬件主要采用对自身整体结构的重配置或者对局部结构的重配置来实现系统的自修复.本文提出了一种数字电路的自重构修复方法,该方法能够以消耗少量的冗余资源为代价获取良好的容错性能.通过实验证明了此演化设计方法运用到容错系统设计中的可行性和有效性.     

可重构系统的演化修复机制

利用演化算法实现系统自修复是一种新的容错设计思路,但是演化是一个非常耗时的过程.已有的演化容错系统多属于静态演化,演化过程仅发生在系统设计阶段,系统在运行过程中不具有演化修复的能力.这类演化容错系统虽然可以避免演化耗时,但是只能修复已知错误,无法修复未知错误.针对上述问题,文中提出一种基于动态演化的修复机制,容错系统采用可重构系统和被检测系统的耦合设计方案.当被检测系统出现故障时,可重构系统通过系统演化实现在线自修复.为了减少演化耗时,系统根据错误类型采取不同措施:如果出现已知错误,系统直接在预置配置库中搜索修复配置;如果出现未知错误,则通过动态演化在线生成修复配置,并更新预置配置库.最后,将该容错设计方案用于典型电路的故障模式.实验结果表明,文中提出的演化修复机制提高了系统运行的实时可靠性,预置配置库设计减少了演化耗时.     

基于TMR-EHW的高可靠性电机控制系统

为提高恶劣环境中控制系统的可靠性,将三模块冗余（TMR）容错与演化硬件（EHW）自修复相结合,实现基于TMR—EHW结构的现场可编程门阵列电机控制系统。该系统利用TMR快速发现和定位故障,屏蔽出错模块并保持容错运行,利用EHW进行自修复,使出错模块恢复正常工作,系统可靠性得到提高。     

演化硬件技术在嵌入式计算机系统中的应用

演化硬件是一个新兴的研究领域,在嵌入式系统中有很多应用,实验证明:应用演化硬件技术中的遗传算法能很好解决嵌入式系统中的软硬件划分问题,而且还可以进行自适应、自修复,开拓了硬件设计自动化的新途径。     

Fault tolerance in co-evolutionary communication of EHW modules

Evolvable Hardware (EHW) is a new concept that applies evolutionary algorithms to hardware design. Based on previous work on co-evolutionary communication of EHW modules, this paper investigates the new feature of fault tolerance for this model. A fault model is built for the communication line between EHW modules. The experiment demonstrated in the presentation is the simulation of injecting stuck/bridging faults into an EHW-based serial adder that has been previously developed. The outcomes imply an outstanding feature of fault tolerance in this system with 100% fault coverage, which paves the way for bio-inspired approaches to fault tolerant design instead of the classic ones.     

On the practicality of using intrinsic reconfiguration for fault recovery

Evolvable hardware (EHW) combines the powerful search capability of evolutionary algorithms with the flexibility of reprogrammable devices, thereby providing a natural framework for reconfiguration. This framework has generated an interest in using EHW for fault-tolerant systems because reconfiguration can effectively deal with hardware faults whenever it is impossible to provide spares. But systems cannot tolerate faults indefinitely, which means reconfiguration does have a deadline. The focus of previous EHW research relating to fault-tolerance has been primarily restricted to restoring functionality, with no real consideration of time constraints. In this paper, we are concerned with EHW performing reconfiguration under deadline constraints. In particular, we investigate reconfigurable hardware that undergoes intrinsic evolution. We show that fault recovery done by intrinsic reconfiguration has some restrictions, which designers cannot ignore.     

Generalized disjunction decomposition for evolvable hardware.

Evolvable hardware (EHW) refers to self-reconfiguration hardware design, where the configuration is under the control of an evolutionary algorithm (EA). One of the main difficulties in using EHW to solve real-world problems is scalability, which limits the size of the circuit that may be evolved. This paper outlines a new type of decomposition strategy for EHW, the "generalized disjunction decomposition" (GDD), which allows the evolution of large circuits. The proposed method has been extensively tested, not only with multipliers and parity bit problems traditionally used in the EHW community, but also with logic circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library and randomly generated circuits. In order to achieve statistically relevant results, each analyzed logic circuit has been evolved 100 times, and the average of these results is presented and compared with other EHW techniques. This approach is necessary because of the probabilistic nature of EA; the same logic circuit may not be solved in the same way if tested several times. The proposed method has been examined in an extrinsic EHW system using the (1 + lambda) evolution strategy. The results obtained demonstrate that GDD significantly improves the evolution of logic circuits in terms of the number of generations, reduces computational time as it is able to reduce the required time for a single iteration of the EA, and enables the evolution of larger circuits never before evolved. In addition to the proposed method, a short overview of EHW systems together with the most recent applications in electrical circuit design is provided.     

一种实现演化硬件的软硬件协同工作模式

演化硬件是一个新兴的研究领域。文章讨论了演化硬件的基本原理,提出了演化硬件实现的四个条件,并对广泛用于实现演化硬件的一种FPGA-XC6200就其特点和结构以及它在实现演化硬件中的应用进行了介绍,并基于这种FPGA芯片给出了一种演化硬件的软硬件协同工作模式。文章最后就演化硬件进一步的研究方向进行了一个总结。     

Real-world applications of analog and digital evolvable hardware

In contrast to conventional hardware where the structure is irreversibly fixed in the design process, evolvable hardware (EHW) is designed to adapt to changes in task requirements or changes in the environment, through its ability to reconfigure its own hardware structure dynamically and autonomously. This capacity for adaptation, achieved by employing efficient search algorithms based on the metaphor of evolution, has great potential for the development of innovative industrial applications. This paper introduces EHW chips and six applications currently being developed as part of MITI's Real-World Computing Project; an analog EHW chip for cellular phones, a clock-timing architecture for Giga hertz systems, a neural network EHW chip capable of autonomous reconfiguration, a data compression EHW chip for electrophotographic printers, and a gate-level EHW chip for use in prosthetic hands and robot navigation     

A Scalable Approach to Evolvable Hardware

Evolvable Hardware (EHW) has been proposed as a new method for designing systems for complex real-world applications. However, so far, only relatively simple systems have been shown to be evolvable. In this paper, it is proposed that concepts from biology should be applied to EHW techniques to make EHW more applicable to solving complex problems. One such concept has led to the increased complexity scheme presented, where a system is evolved by evolving smaller sub-systems. Experiments with two different tasks illustrate that inclusion of this scheme substantially reduces the number of generations required for evolution. Further, for the prosthesis control task, the best performance is obtained by the novel approach. The best circuit evolved performs better than the best trained neural network.     

一种基于GEP的演化硬件复杂电路优化算法

演化硬件是近年来新兴的研究热点,它是演化算法和可编程逻辑器件相结合而形成的硬件设计新方法。在演化硬件中门电路的优化设计是一个重要的研究领域。提出一种新的基于基因表达式程序设计（GEP）的算法来进行复杂优化电路的设计,通过仿真实验表明,该算法不仅收敛速度快,而且还能利用该算法优化大规模的门电路,克服了传统优化方法的求解速度慢甚至不收敛等缺点。该算法较传统的电路优化方法更简单、更高效。     

基于基因表达式的演化硬件进化和优化算法

电路进化设计是可进化硬件研究的重要内容．针对电路进化设计做了如下工作：(1)融合了数据挖掘、基因表达式编程与传统电路进化技术,提出两阶段电路进化方法．该方法包括基于表达式树遗传编程进化算法的电路进化阶段和基于挖掘频繁数字电路算法的电路优化阶段。(2)给出了详尽的实验．实验表明6次多项式函数发现的平均进化代数为442代、乘法器电路的平均进化代数为2292代．比笛卡尔遗传编程和NEHF(Novel Evolvable Hardware Framework)快6倍以上．用MFDC对乘法器电路进化结果进行挖掘后,得到了比传统电路更有效的乘法器电路。     

A projection-based decomposition for the scalability of evolvable hardware

Scalability is a main and urgent problem in evolvable hardware (EHW) field. For the design of large circuits, an EHW method with a decomposition strategy is able to successfully find a solution, but requires a large complexity and evolution time. This study aims to optimize the decomposition on large-scale circuits so that it provides a solution for the EHW method to scalability and improves the efficiency. This paper proposes a projection-based decomposition (PD), together with Cartesian genetic programming (CGP) as an EHW system namely PD-CGP, to design relatively large circuits. PD gradually decomposes a Boolean function by adaptively projecting it onto the property of variables, which makes the complexity and number of sub-logic blocks minimized. CGP employs an evolutionary strategy to search for the simple and compact solutions of these sub-blocks. The benchmark circuits from the MCNC library, \(n\)-parity circuits, and arithmetic circuits are used in the experiment to prove the ability of PD-CGP in solving scalability and efficiency. The results illustrate that PD-CGP is superior to 3SD-ES in evolving large circuits in terms of complexity reduction. PD-CGP also outperforms GDD+GA in evolving relatively large arithmetic circuits. Additionally, PD-CGP successfully evolves larger \(n\)-even-parity and arithmetic circuits, which have not done by other approaches.