44 Gbit/s GaAs MESFET selector IC

A novel 2:1 selector circuit is described. To achieve high-speed operation, a parallel feedback circuit and inductor peaking were added to a conventional selector circuit. Furthermore, wide bandwidth buffers are carefully designed to cover the operation frequency of this selector circuit. The selector IC, fabricated with 0.1 μm class GaAs MESFETs, operated at up to 44 Gbit/s     

Low-power 100 Gbit/s selector IC using InP/InGaAs DHBTs

A low-power 100 Gbit/s selector IC using InP DHBTs, which provides excellent high-frequency characteristics at a low bias condition, is reported. A novel design technique, which assists high-speed operation under a low supply voltage condition, is used. The selector IC achieves 100 Gbit/s operation with a power consumption as low as 345 mW.     

A distributed selector IC using GaAs MESFET's withmultilayer-interconnection structure

This paper describes novel high-speed selector circuits based on the distributed circuit approach and their circuit design methodologies. Two types of distributed selectors are designed and fabricated using 0.16 μm GaAs MESFET's with multilayer-interconnection structure. Both basically consist of eight stages of series-gated source-coupled field-effect transistor (FET) logic (SCFL) selector cell units laid out in a distributed fashion. The second circuit incorporates additional functions: a data input level shifter in each cell to make an SCFL interface for the data input and a balun for single-balance transformation of the clock input. A small-signal distributed amplifier design is extended to a large-signal distributed logic IC design, taking dynamic variations in transistor parameters into consideration. The error-free operation of both fabricated distributed selector IC's is confirmed at up to 40 Gbit/s, and the first IC still exhibited eye opening with 130 mV voltage swing of the inside measurement at 70 Gbit/s, which reaches 80% of f_T of the fabricated FET. These distributed selector IC's successfully exhibit eye opening at higher bit rates compared to the conventional lumped-element design selector     

一种基于声光开关的小型化高速脉冲单选器设计

重点介绍了声光开关与光脉冲单选器的基本工作原理,设计了一种以声光开关为核心器件的小型化高速脉冲单选器,该脉冲单选器具有消光比高、插入损耗低、性能稳定和结构小等特点,可用于从锁模激光器输出光脉冲串中选取单个光脉冲作为前端系统的种子光源。     

30Gbit/s并行光接收模块

报道了一种基于CMOS工艺接收电路芯片和GaAs工艺1×12光电探测器阵列的30Gbit/s并行光接收模块.该模块采用并行光通信方案,利用中高速光电子器件实现信号的高速传输.直接使用未经封装的接收电路裸片和光探测器裸片,采用电路板上芯片技术封装制作模块,并通过倒装焊的方式实现了探测器阵列与列阵光纤的精确对准并形成了可插拔的光接口.测试结果表明模块的接收能力可以达到30Gbit/s.误码率小于10-13时,接收模块的灵敏度可以达到-13.6dBm.     

30Gbit/s Parallel Optical Receiver Module

报道了一种基于CMOS工艺接收电路芯片和GaAs工艺1×12光电探测器阵列的30Gbit/s并行光接收模块.该模块采用并行光通信方案,利用中高速光电子器件实现信号的高速传输.直接使用未经封装的接收电路裸片和光探测器裸片,采用电路板上芯片技术封装制作模块,并通过倒装焊的方式实现了探测器阵列与列阵光纤的精确对准并形成了可插拔的光接口.测试结果表明模块的接收能力可以达到30Gbit/s.误码率小于10-13时,接收模块的灵敏度可以达到-13.6dBm.     

A 40-GHz D-type flip-flop using AlGaAs/GaAs HBT's

We report master-slave D-type flip-flop (D-FF) circuit implemented with AlGaAs/GaAs HBT's. The fabricated HBT's had an f_T of 107 GHz and an f_max of 110 GHz. To maximize the speed, the logic swing and transistor size in the IC were optimized. In the D-FF, to facilitate the high-speed testing, a selector circuit was integrated on the same chip. As a result, the operation of this IC was confirmed up to 40 GHz, which is the highest speed in D-FF     

28 Gbit/s selector IC using AlGaAs/GaAs HBTs

An ultra-high-speed selector IC has been developed for future optical transmission systems. The IC was fabricated with AlGaAs/GaAs HBT technology, for which the f/sub T/ is about 70 GHz. It operates at 28 Gbit/s with an output voltage swing of 1 V/sub p-p/. This is the fastest operating speed ever reported for a selector IC using any technology.<>     

100-Gb/s multiplexing and demultiplexing IC operations in InP HEMT technology

This paper describes the 100-Gb/s multiplexing operation of a selector IC and demultiplexing operation of a D-type flip-flop (D-FF) using production-level 0.1-/spl mu/m-gate-length InP HEMT IC technology. To boost the operating speed of the selector IC, a selector core circuit directly drives an external 50-/spl Omega/ load, and is included in the output stage. In addition, a test chip containing the selector and a D-FF to confirm error-free operation of these circuits was designed. The fabricated selector IC exhibited clear eye openings at 100 Gb/s, and its error-free operation was confirmed by using the test chip.     

A 60-GHz fT super self-aligned selectively grownSiGe-base (SSSB) bipolar transistor with trench isolation fabricated onSOI substrate and its application to 20-Gb/s optical transmitterICs

A 60-GHz cutoff frequency (f_T) super self-aligned selectively grown SiGe-base (SSSB) bipolar technology is developed. It is applied to 20-Gb/s optical fiber transmitter ICs. Self-aligned bipolar transistors mutually isolated by using a BPSG-filled trench were fabricated on a bond-and-etchback silicon-on-insulator (SOI) substrate to reduce the collector-substrate capacitance C_CS. The SiGe base was prepared by selective epitaxial growth (SEG) technology. A 0.4-μm wide emitter was used to reduce the junction capacitances. The maximum cutoff frequency f_T and the maximum frequency of oscillation f_max were 60 and 51 GHz, respectively. By using this technology, Si-ICs for an optical transmitter system were made, such as a selector (a multiplexer without input and output retiming D-type flip-flops (D-F/Fs)), a multiplier, and a D-F/F. An internal high-speed clock buffer circuit achieves stable operation under a single clock input condition in the selector and the multiplier ICs. Their stable operation was confirmed up to 20 Gb/s. The selector IC for data multiplexing operates at over 30 Gb/s     

基于RISC技术的实现单字节乘法的MCU设计

基于RISC技术实现单字节乘法的微控制器设计主要包括：RISC指令集的选取、取指单元、译码单元、执行单元的设计.该微控制器包含8个模块：8位指令存储器、12位程序计数器、12位地址选择器、可进行16位加法的算术运算器、16位累加器、16选8的数据选择器、8位数据控制器以及状态机.为了进行测试,又增加了3个外围模块：RAM,ROM和addr_decode.设计使用可综合的Verilog 语言描述,Modelsim 5.7 PE软件仿真.     

A 1.5 Gbit/s GaAs four-channel selector LSI with monolithicallyintegrated newly structured GaAs ohmic contact MSM photodetector andlaser driver

A monolithic integrated 1.5 Gb/s high-speed four-channel optoelectronic integrated circuit (OEIC) selector GaAs LSI circuit is discussed. This LSI circuit incorporates photodetectors, preamplifiers, a selector, a decision circuit, and a high-speed laser driver. To achieve high efficiency, a AuGe/Ni-GaAs structured ohmic contact metal-semiconductor-metal (OC-MSM) is used for the interdigitated structural photodetector. With this OC-MSM structure, photocurrent is approximately twice as effective as with the conventional Schottky contact MSM structure. The new LSI has a maximum operating speed of 1.5 Gb/s and exhibits low power dissipation of 927 mW     

1 Gbit/s, 32*32 high-speed space-division switching module for broadband ISDN using SST LSIs

A high-speed 32*32 space-division switching module for high-definition TV broadcasting and switching systems is described. It employs a newly developed Si-bipolar SST 8*8 switch LSI, high-speed peripheral ICs and a high-speed impedance-controlled board. The module is capable of a 1.0 Gbit/s signal speed using 1:1 and 1:n connections.<>     

1.25/10.3 Gbit/s dual-rate burst-mode receiver

A 1.25/10.3 Gbit/s dual-rate burst-mode receiver is proposed, which uses a tunable lowpass filter to change the sensitivity for each bit rate and an output-port selector to switch the output port according to the input bit rate. It is demonstrated that this receiver can realise a high sensitivity, a wide dynamic range, and a high-speed response with long consecutive identical digit signals.     

Packaging technology for a 10-Gb/s photoreceiver module

We designed a 10-Gb/s photoreceiver module integrating a flip-chip avalanche photodiode (APD), a Si-preamplifier IC, and a slant-ended fiber (SEF). Flip-chip bonding minimizes parasitic reactances in the interconnect between the photodiode and the preamplifier IC. The optical coupling system consists of a slant-ended fiber and a microlens monolithically fabricated on the photodiode. This gives a flat IC-package assembly, which enables stripline interfaces to extract high-speed signals, increases misalignment tolerances, and lowers package height. Tolerances of over ±9 μm were obtained in every direction, which matched our theoretical predictions. To attach and hermetically seal the optical coupling, the fiber ferrule was directly laser-welded to the package wall with a double ring structure. The module withstood shock and vibration tests and had a 10-GHz bandwidth and -23-dBm minimum photosensitivity at 10 Gb/s     

3G手机高速串行接口液晶显示模块的设计与应用

高速串行接口由于在EMI、体积和功耗等方面的特性,在要求不断提高的3G手机液晶显示模块上的应用也愈发体现出其优势.介绍了一种目前主流的高速串行接口-MDDI的物理层和数据连结层的结构和原理,开发了基于三星S6D0139芯片的带MDDI接口的液晶显示模块.利用该模块实现了主副屏的静态画面显示和主屏的动态视频显示.经过实际的测试,证实采用高速串行接口的模块在保持原有显示效果的基础上.在接口的体积以及电磁兼容等性能上相对于传统的LCD接口有明显的优势,能更好地适应3G手机高速视频数据传输的需要.     

SRAM灵敏放大器的设计改进及其Hspice仿真分析

静态随机存取存储器（SRAM）由于其自身的低功耗和高速的优势而成为半导体存储器中不可或缺的重要产品。提高和改善静态存储器的性能依然是集成电路设计领域的重要课题。从降低静态存储器功耗的角度出发，重点研究了静态存储器的关键模块——灵敏放大器的工作机理和结构，设计了一种改进型的锁存型灵敏放大器，Hspice的仿真表明，该放大器的功耗大大低于传统的静态存储器的灵敏放大器模块的功耗。     

A SiGe BiCMOS analog SISO decoder with I/O interface

Although recent implementations of analog iterative decoders have proven their potential for higher decoding speed and less power consumption than their digital counterparts, the CMOS or conventional BiCMOS technologies used so far seem to be incapable to cope with the need for high throughput that high-speed applications require. Within this context this work presents the design and test results of a high-speed analog SISO (Soft-Input Soft-Output) channel decoder for an 8-bit trellis code by exploiting the high-speed features of SiGe heterojunction bipolar transistors (HBTs). It is one of the first successful implementations of an error-correcting decoder in SiGe BiCMOS technology, which incorporates a high-speed I/O interface. A high-level model of the mismatch effects indicates that there is no significant performance penalty. Moreover, simulations and performance evaluations of an analog Turbo decoder based on the designed SISO decoder are provided. Even though the IC of the SISO module was tested at a throughput up to 3 Mbps, simulation results show that the decoder is capable to operate at 50 Mbps. The measured power consumption is 860 mW and the die area is 3.4 × 3 mm².     

Over 80 Gbit/s 2:1 multiplexer and low power selector ICs using InP/InGaAs DHBTs

A 2:1 multiplexer (MUX) and low power selector ICs have been successfully designed and manufactured using an InP/InGaAs DHBT technology. The 2:1 MUX has been tested at data rates up to 80 Gbit/s with an output swing of 600 mV, while the selector IC has achieved operation speed up to 90 Gbit/s at a power consumption of only 385 mW.     

Realization of a discrete Fourier transform (DFT) module for incorporation in FFT processors

For applications requiring high-speed and in-place treatment, it is often advantageous to realize special-purpose computers. This paper describes a discrete Fourier transform (DFT) module for incorpration in fast Fourier transform (FFT) processors. The module is highly suitable for real input applications requiring high-speed transformations. It attributes one point to all frequency channels in one clock cycle. This treatment is not only well suited for the present technology, but appears to be more attractive in view of recent trends in digital circuitry.