A multilevel inverter based on cascade connection of submultilevel units with reduced switch count

In this paper, a multilevel inverter based on cascade connection of new submultilevel inverters is presented. The suggested submultilevel inverter is constructed using series connection of basic switching units. The proposed multilevel inverter uses fewer power switches in comparison with some similar topologies which results in reduction of switch gate drivers and also converter size and cost. The proposed multilevel inverter can be implemented in both symmetric and asymmetric configurations. The multilevel inverter configuration and operation principle are described in detail, and then, design methods of symmetric and asymmetric configurations are given. Determination of the optimal number of basic units and cascaded submultilevel inverters regarding criteria such as number of switches and total blocking voltage (TBV) of switches is studied. Power losses of the proposed multilevel inverter are calculated, and then, its symmetric and asymmetric configurations are compared with each other and also with similar cascaded multilevel inverters in various items. The validity of the suggested cascaded multilevel inverter is verified using both computer simulations and laboratory prototype implementation.     

一种基于开关电容的单电源升压型六电平逆变器

针对现有开关电容型多电平逆变器存在拓扑结构复杂、器件数量较多、电容电压不平衡以及电压应力较大等缺点,提出一种新型的基于开关电容的六电平逆变器。该电路拓扑由6个功率开关、1个直流电压源和3个电容组成,可以产生2.5倍升压增益的六电平输出电压。此外,由于电容由输入直流电压源直接充电至固定电压,因此电容电压能够实现自动平衡。对所提逆变器的工作原理、PWM调制策略以及电路参数等方面进行详细分析,同时还对该逆变器与现有多电平逆变器进行了对比研究。最后采用Matlab软件建立了仿真模型,仿真结果验证了所提电路的有效性和可行性。     

An FPGA-based switching photovoltaic-connected inverter topology for leakage current suppression in grid-connected utilizations

This study presents a symmetrical photovoltaic (PV)-connected inverter topology for eliminating the common-state leakage current in grid-connected inverters. A new inverter topology is introduced that minimizes the leakage current, increases efficiency, and is economically viable because it consists of six power switches and two power diodes that, compared with similar ones, consist of the same element numbers. In this inverter, power losses are lower than popular topologies such as H5, H6, and HERIC, and the voltage stresses of the switches are reduced. These features are due to the unique composition of the inverter branches and the location of the switches and diodes and the formation of a suitable freewheeling path for the current. The freewheeling path separates the alternating current (AC) side from the direct current side in the converter and cuts off the PV array leakage current to the AC grid. This will improve network reliability indices and maintain conservation standards. Finally, the content of this method is validated by comparing the proposed inverter with the existing conventional topologies. A prototype has been implemented for the performance analysis of the proposed inverter and results presented.     

Multilevel DC-link inverter

This paper presents a new class of multilevel inverters based on a multilevel dc link (MLDCL) and a bridge inverter to reduce the number of switches, clamping diodes, or capacitors. An MLDCL can be a diode-clamped phase leg, a flying-capacitor phase leg, or cascaded half-bridge cells with each cell having its own dc source. A multilevel voltage-source inverter can be formed by connecting one of the MLDCLs with a single-phase bridge inverter. The MLDCL provides a dc voltage with the shape of a staircase approximating the rectified shape of a commanded sinusoidal wave, with or without pulsewidth modulation, to the bridge inverter, which in turn alternates the polarity to produce an ac voltage. Compared with the cascaded H-bridge, diode-clamped, and flying-capacitor multilevel inverters, the MLDCL inverters can significantly reduce the switch count as well as the number of gate drivers as the number of voltage levels increases. For a given number of voltage levels m, the required number of active switches is 2/spl times/(m-1) for the existing multilevel inverters but is m+3 for the MLDCL inverters. Simulation and experimental results are included to verify the operating principles of the MLDCL inverters.     

一种光伏发电用高增益多电平逆变器

针对传统的多电平逆变器存在有源器件数量较多、电容电压不平衡、结构复杂以及电压增益低的问题,提出一种降低器件数量且可扩展的多电平逆变器。该逆变器由开关电容单元和两个半桥组成,使用1个直流电源、3个电容、13个开关管,实现4倍电压增益和九电平交流输出电压。该逆变器通过2个半桥代替后端H桥转换输出电压极性,可以有效降低开关管总电压应力。在所提逆变器的扩展结构中,电容逐级充电的工作方式进一步提高了电压增益和输出电平数。首先,详细阐述了所提逆变器的工作模式、调制策略、电容分析、电压应力计算和电路参数设计。然后,与其他类似多电平逆变器进行了比较。最后,通过仿真与实验验证了所提逆变器的可行性和理论分析的正确性。     

FPGA控制的不对称多电平逆变器的设计

随着多电平技术在大容量场合的应用,不同结构的多电平拓扑结构不断被提出。论文研究一种混合级联式不对称多电平逆变器,该结构逆变器将传统H桥逆变器进行改进,与H桥相比使用相同器件时,该结构能够输出更多的电平数,或者在输出相同电平数的情况下比传统H桥级联结构使用更少的器件。该多电平逆变器由两个不对称四电平逆变器级联而成,输出电...     

A bidirectional diode containing multilevel inverter topology with reduced switch count and driver

In this paper, a bidirectional diode containing multilevel inverter is introduced to reduce the number of switching elements especially in the case of a high number of output voltage levels. In comparison with classic and recently introduced symmetrical topologies, which are trying to reduce the switch count, this topology has a lower number of semiconductor switches in the same number of output voltage levels. This makes the proposed inverter to be a suitable choice for medium voltage applications like renewable energy applications as well as medium voltage electric drives. Moreover, it can be used in a cascaded configuration for high voltage levels. To depict the performance of the proposed structure, a comprehensive comparison is made between this topology and classic and recently proposed symmetric topologies in terms of switch and gate driver count, power losses, and cost. The performance of the proposed symmetrical 11-level converter is analyzed and simulated in MATLAB/Simulink for both PWM and selective harmonic elimination switching methods. Not only the results are desirable but also the experimental results of laboratory prototype validate the simulation results.     

选择性谐波消除法在多电平逆变器故障调制中的应用

随着多电平逆变器应用的增多,其开关故障运行控制问题也尤为突出。将选择性谐波消除法SHE(selective harmonic elimination)应用到多电平逆变器的容错控制中,提出一种提高系统可靠性的新型方法。利用SHE方法通过只屏蔽故障单元,不降低非故障相逆变器的容量进行容错。原来的SHE方法只能修正电压幅值,通过改进SHE来修正相移角的容错控制方法,可以使逆变器输出均衡的线电压和负载电压。提出的SHE方法容错控制适用于多电平逆变器的不同拓扑结构,对逆变器的低次谐波消除效果较好,补偿谐波具有灵活性和实用性。仿真和实验结果验证了提出方案的有效性。     

一种混合级联型多电平逆变器拓扑结构

在交流电动机调速领域,大容量多电平变换器的应用越来越广泛,为了改善系统性能,各种各样的多电平拓扑结构被提出.本文提出了一种新颖的混合级联式多电平拓扑结构,该结构将传统的H桥逆变器(主逆变器)和二极管钳位型三电平逆变器(从逆变器)结合起来,串联为电动机供电,而这其中仅仅只有主逆变器需要电压源.这种新型的拓扑结构由于增加了从逆变器作为辅助单元用于能量存储,可以提高系统的效率,一定程度上实现电动机的四象限运行.相比传统的H桥逆变器,该拓扑可以减少输入电压源的数目;当电动机以稳定速度运行时,从逆变器可以为负载提供无功能量.该拓扑结构在电力机车和大型舰船推进系统等领域有着广泛的应用前景.     

A new structure of single-phase two-stage hybrid transformerless multilevel PV inverter

Transformerless inverters are becoming popular for grid-connected photovoltaic applications due to their simplicity, reduced size, weight, cost, and higher efficiency. In this paper, a two-stage hybrid transformerless multilevel inverter (MLI) for single-phase grid-connected photovoltaic power generation system (PVPGS) is presented. The proposed topology comprises a multilevel boost converter (MLBC) and a symmetrical hybrid MLI. MLBC combines the boosting and switched capacitor voltage functions to produce self-balanced multiple voltage levels. The proposed MLI is derived from a combination of bidirectional switches, a half bridge, and a diode-clamped branch, which can produce only two variations in the total common mode voltage and is capable of suppressing leakage current as per DIN VDE 0126-1-1 grid standards. It offers the advantages of scalability, reactive power capability, reduced total harmonic distortion, and filter size. The proposed hybrid transformerless seven-level inverter is simulated in MATLAB, and experimental setup is built to validate the effectiveness of the proposed configuration. Finally, a comprehensive comparison is made with other seven-level inverter topologies.     

Cascaded Multilevel Inverters Using Proposed Series Sub-multilevel Basic Blocks with Reduced Switching Devices

In this paper, a novel configuration of the cascaded multilevel inverters using series connection of new sub-multilevel basic blocks is presented. The basic structure of the proposed sub-multilevel inverter is made of three isolated batteries and eight unidirectional power switches. Hereby, by changing the polarity of one of such batteries and two power switches, two different modules of sub-multilevel inverters can be extracted that each of them is able to be incorporated into two different cascaded structures as the series basic blocks. Contemporary, to determine the suitable magnitudes of the integrated batteries, two different algorithms for each topology along with their relevant mathematical analysis have been also given. In this study, a complete comparison between the proposed topologies and several recently presented structures has been conducted. The compiled comparisons can prove the fact that both the proposed cascaded inverters are capable of generating a higher number of output voltage levels with less number of switching counts. Other advantages of these structures are reduction of voltage sources numbers, DC sources variety, value of total blocking voltage, and also conducting losses. In order to demonstrate the correct operation of the proposed structures and presented algorithms, some experimental results will be also shown.     

A new generalized switched diode multilevel inverter topology with reduced switch count and voltage on switches

This article presents a new multilevel inverter topology with reduced power switches. The proposed topology composes of several series connection of basic unit for obtaining a required output voltage level. The proposed topology can operate in symmetric condition. The proposed topology is connected in a cascaded structure to produce a higher number of output voltage levels. The proposed cascaded structure is optimized with the minimum number of components for the maximum number of levels. To prove the superiority of the proposed multilevel inverter topology, different technical parameter comparisons are carried out with recently developed multilevel inverter topologies from the literature. The calculation of total standing voltage is examined for the proposed topology. The operation of the proposed topology is tested and verified for nine-level output voltage. The simulated results are carried out, and it is strengthened by the real-time prototype results.     

一类单相电流型多电平逆变器拓扑及其PWM方法的研究

现有的关于多电平逆变器的研究工作主要是针对电压型多电平逆变器(VSI)，电流型多电平逆变器(CSI)的研究成果较少。该文提出了一类单相多电平CSI拓扑，结构简单，所用开关器件数和分流电感数较少；由于拓扑具有自均流特性，即使在电路器件非理想的情况下，无需闭环控制仍然可以实现电流的均衡。文中分析了该类5电平拓扑的工作原理以及分流电感的自均流原理；通过引入多载波POD SPWM 技术，给出了该技术在该类拓扑中的具体实现方法。文中最后给出了仿真和实验结果。     

Improved Configuration of Multilevel Inverter with Reduced Semiconductor Devices

In DC/AC power conversion, multi-level inverter (MLI) incorporates a large number of semiconductor devices, which increases its cost and complexity. Moreover, the recently introduced topology uses a large variety of semiconductor switches. Therefore, a great attention is paid toward increasing output voltage levels with less variety and reduced number of switches as compared to conventional topologies. In this paper, improved configuration of symmetrical and asymmetrical MLI is proposed. Improvement is brought on both quantitative and qualitative basis, which led to a reduction in number of semiconductor devices and its variety. Analysis of power losses of the proposed topology is carried out and compared with CHB. A wide range of comparison with recently proposed topologies is made in order to show the novelty and contribution of the proposed topology. Multi-Carrier Pulse Width Modulation strategy is adopted for generating the switching pulses. The detailed simulation study of the proposed topology has been carried out using MATLAB/SIMULINK and validated experimentally for 7-level and 81-level inverter.     

PWM控制下多电平混合逆变电路的脉宽调制及拓扑分析

PWM和多电平变换是在高压大功率电力电子变换中应用较多的两种技术 ,本文在试验一种新型混合逆变电路的基础上 ,通过分析PWM控制下的多电平混合逆变电路调制方法 ,提出了一种混合单元间电压比取值的方法 ,理论上试图涵盖可能出现的混合逆变电路拓扑     

PWM Inverters Using Split-Wound Coupled Inductors

The number of output-voltage levels available in pulsewidth-modulated (PWM) voltage-source inverters can be increased by inserting a split-wound coupled inductor between the upper and lower switches in each inverter leg. Interleaved PWM control of both inverter-leg switches produces three-level PWM voltage waveforms at the center tap of the coupled inductor winding, representing the inverter-leg output terminal, with a PWM frequency twice the switching frequency. The winding leakage inductance is in series with the output terminal, with the main magnetizing inductance filtering the instantaneous PWM-cycle voltage differences between the upper and lower switches. Since PWM dead-time signal delays can be removed, higher device switching frequencies and higher fundamental output voltages are made possible. The proposed inverter topologies produce five-level PWM voltage waveforms between two inverter-leg terminals with a PWM frequency up to four times higher than the inverter switching frequency. This is achieved with half the number of switches used in alternative schemes. This paper uses simulated and experimental results to illustrate the operation of the proposed inverter structures.      

A three-phase inverter circuit using half-bridge cells and T-NPC for medium-voltage applications

Three-phase single DC-source based multilevel inverter topologies play a pivotal role in industrial applications due to the reduced number of components and higher efficiency. This paper emphasizes the inverter for medium-voltage applications that employ a conventional three-phase T-type structure (T-NPC). The primary circuit of the proposed configuration consists of a T-NPC structure connected to the half-bridge cells at the top and the bottom sides of each phase. The secondary circuit consists of DC-link capacitors whose voltage balancing is attained through a separate voltage balancing circuit (VBC). Using the proposed configuration, the number of components and independent DC supplies are reduced compared with the conventional topologies such as a neutral point clamped (NPC) inverter, a flying capacitor (FC) inverter, and a cascaded H-bridge (CHB) inverter for the same number of output voltage levels. Hence, the proposed topology results in the reduction of weight, volume, and power losses of the inverter. A sine-triangle comparison method is employed in the field programmable gate array (FPGA) platform to generate the firing pulses of the circuit switches. The effectiveness of the proposed topology is verified with simulation studies and is experimentally validated with a scaled-down prototype.     

A New Cascaded Multi-level Inverter Topology with Reduced Number of Components and Charge Balance Control Methods Capabilities

In this article, a new basic unit for cascaded multi-level inverter is proposed. This inverter is able to increase the number of output voltage levels and reduces the number of power electronic devices. To generate all voltage levels at the output, five different algorithms to determine the magnitude of DC voltage sources are suggested. This inverter is compared with conventional cascaded multi-level inverters. The comparisons show that the proposed topology needs fewer DC voltage sources and power switches, less variety of the magnitude of DC voltage sources, and smaller amounts of blocked voltage by switches. As a result, the installation space and total cost of the inverter decrease. As it is impossible to use charge balance control methods for the asymmetric cascaded multi-level inverters, the developed topology based on the proposed cascaded inverter–the sub-symmetric topology with the usability of charge balance control methods–is proposed. A new algorithm is proposed to determine the magnitude of DC voltage sources. In addition, full-wave and half-wave charge balance control methods are applied in the proposed developed topology. The accurate performance of the proposed topology by applying charge balance control methods is verified through the simulation and experimental results of an 81-level sub-symmetric inverter.     

一种低漏电流六开关非隔离全桥光伏并网逆变器

为满足非隔离光伏并网发电系统对共模漏电流的限制,提出一种六开关逆变器拓扑(H6拓扑)。所提出的H6拓扑在功率传输模态时,进网电流半个工频周期流过3支开关管,而另半个工频周期流过2支开关管,故相对于H5拓扑,降低了通态损耗,有利于热应力均衡,且仍满足续流阶段光伏电池输出端与电网脱离的要求。详细分析拓扑的工作原理,并推论给出H6非隔离光伏并网逆变器的其它3种拓扑结构;比较分析了H5拓扑、Heric拓扑和H6拓扑的损耗和成本。通过1kW通用样机平台对比验证了上述3种拓扑的效率和共模特性。实验结果表明,H6拓扑的变换效率高于H5拓扑、但略低于Heric拓扑,共模特性优于Heric拓扑、但略劣于H5拓扑。     

Fault-tolerant switched capacitor–based boost multilevel inverter

This paper proposes a fault-tolerant switched capacitor (SC)–based boost multilevel inverter. The proposed inverter is able to convert a low-level dc voltage into a desired ac output voltage in single-stage power conversion. It can accomplish a high voltage gain by using multiple SC cells arrangement at reduced voltage stresses on the switching devices and passive circuit elements in the boost network. The principle of operation and steady-state analysis of the proposed topology are presented to formulate the mathematical relationship between input dc and output ac voltage. In addition to that, the proposed inverter can also provide reliable electrical power supply at prescribed ac output voltage in the event of open-circuit failure of power switches. The fault tolerability is realized by reconfiguring the pulse width modulation (PWM) control scheme, whereas the reduction in output voltage is compensated by the boosting characteristic of the inverter. The effectiveness of the proposed inverter has been compared with other impedance source multilevel inverters in terms of voltage gain, boosting capability, and voltage stresses. A laboratory prototype of the proposed inverter is developed for experimentation, and its operation is validated by simulation and experimental results.