Reliability evaluation of ultra-thin CSP using new flip-chip bonding technology––double-sided CSP and single-sided CSP

A high-density packaging technology has been developed that uses new flip-chip bonding technology with a thin IC and a thin substrate. Numerical analysis with the finite element method as well experiments clearly showed that deflection of the IC and reliability were affected by the IC thickness. Consequently, reliability could be improved by reducing IC thickness. The dependency of the life in single-sided chip-size packages (CSPs) could be expressed using a normal stress value in thickness, which is computed by the IC thickness and substrate type and thickness. The dependency of the life in double-sided CSPs could be expressed using a shear stress value in the vertical cross section, which is computed in IC thickness and substrate type and thickness, respectively.Moreover, a double-sided flip-chip approach solved the problem of warpage. A high-capacity memory card of 512 MB was put to practical use by applying these results. This increased the Si density by four times over that of a conventional CSP.     

Visco-elastic-plastic properties and constitutive modeling ofunderfills

The thermo-mechanical testing of HYSOL PP4526 underfill is reported, including the details of sample preparation and test procedures. It is found that the Young's modulus of the underfill depends on both temperature and applied strain rate. The constitutive framework proposed for solder alloys has been applied successfully to model the thermo-mechanical properties of the underfill in this paper. Excellent agreement between model predictions and experimental data is achieved, The test data and calibrated constitutive model can be used for the analysis and design of advanced electronic packages with underfills such as flip-chip packages     

微波倒装焊互连技术及特性分析

随着应用频率的提高,微波芯片与基板间的互连更多地采用了倒装焊。文中用HFSS（高频结构仿真器）有限元软件对凸点变换及倒装互连结构进行建模、仿真和优化,提取了凸点变换的等效集总电路模型,介绍了凸点制作工艺和倒装焊结构互连的微组装过程,并完成了试验样品的测试。最后,对微波倒装焊的前景进行了展望。     

Improved Light Extraction of Nitride-Based Flip-Chip Light-Emitting Diodes Via Sapphire Shaping and Texturing

A novel flip-chip structure of GaN-sapphire light-emitting diodes (LEDs) was developed to improve the external quantum efficiency, where the sapphire substrate was textured and shaped with beveled sidewalls using a wet etching technique. The forward voltage of the conventional flip-chip and shaped flip-chip GaN LEDs were 2.84 and 2.85 V at 20 mA, respectively. This indicates that the GaN LED was not destroyed during the sapphire wet etching process. It was found that the output power increased from 9.3 to 14.2 mW, corresponding to about 52% increases in the external quantum efficiency. The results agree well with the simulation data that the shaped flip-chip GaN LED can provide better light extraction efficiency than that of the conventional flip-chip sample     

Novel reworkable fluxing underfill for board-level assembly

Underfills are traditionally applied for flip-chip applications. Recently, there has been increasing use of underfill for board-level assembly including ball grid arrays (BGAs) and chip scale packages (CSPs) to enhance reliability in harsh environments and impact resistance to mechanical shocks. The no-flow underfill process eliminates the need for capillary flow and combines fluxing and underfilling into one process step, which simplifies the assembly of underfilled BGAs and CSPs for SMT applications. However, the lack of reworkability decreases the final yield of assembled systems. In this paper, no-flow underfill formulations are developed to provide fluxing capability, reworkability, high impact resistance, and good reliability for the board-level components. The designed underfill materials are characterized with the differential scanning calorimeter (DSC), the thermal mechanical analyzer (TMA), and the dynamic mechanical analyzer (DMA). The potential reworkability of the underfills is evaluated using the die shear test at elevated temperatures. The 3-point bending test and the DMA frequency sweep indicate that the developed materials have high fracture toughness and good damping properties. CSP components are assembled on the board using developed underfill. High interconnect yield is achieved. Reworkability of the underfills is demonstrated. The reliability of the components is evaluated in air-to-air thermal shock (AATS). The developed formulations have potentially high reliability for board-level components.     

Flip-chip bonding optimizes opto-ICs

The development of fabrication techniques for optical components and hybrid assemblies based on flip-chip bonding is outlined. It is argued that the solder-bump technique offers self-alignment, ruggedness, and potentially low manufacturing cost to integrated optics, semiconductor lasers, and optical interconnect devices. Examples of applying flip-chip solder bonding to these devices are presented     

A new flip-chip bonding technique using micromachined conductivepolymer bumps

Using micromachining techniques with thick photoresists, a new conductive polymer flip-chip bonding technique that achieves both a low processing temperature and a high bumping alignment resolution has been developed in this work. By the use of UV-based photolithography with thick photoresists, molds for the flip-chip bumps have been patterned, filled with conductive polymers, and then removed, leaving molded conductive polymer bumps. After flip-chip bonding with the bumps, the contact resistances measured for 25 μm-high bumps with 300 μm×300 μm area and 400 μm×400 μm area were 35 mΩ and 12 mΩ respectively. The conductive polymer flip-chip bonding technique developed in this work shows a very low contact resistance, simple processing steps, a high bumping alignment resolution (<±5 μm), and a lower bonding temperature (~170°C). This new bonding technique has high potential to replace conventional flip-chip bonding technique for sensor and actuator systems, bio/chemical μ-TAS, optical MEMS, OE-MCM's, and electronic system applications     

Evaluation and optimization of package processing and design through solder joint profile prediction

Solder joints are generated using a variety of methods to provide both mechanical and electrical connection for applications such as flip-chip, wafer level packaging, fine pitch, ball-grid array, and chip scale packages. Solder joint shape prediction has been incorporated as a key tool to aid in process development, wafer level and package level design and development, assembly, and reliability enhancement. This work demonstrates the application of an analytical model and the Surface Evolver software in analyzing a variety of solder processing methods and package types. Bump and joint shape prediction was conducted for the design of wafer level bumping, flip-chip assembly, and wafer level packaging. The results from the prediction methodologies are validated with experimentally measured geometries at each level of design.     

PtSi 256×256 IRCCD微型化封装技术研究

采用倒装焊接技术,实现了PtSi 256×256 IRCCD微型化封装。对金属凸点、引线衬底的制备以及倒装焊接技术进行了研究。     

混成式焦平面阵列芯片倒装互连技术研究

介绍了为保证倒装焊接性能,设备所采取的措施。对比了不同形貌铟柱的优缺点,分析了互连可靠性与铟柱高度的关系,介绍了考核互连可靠性的方法。通过互连技术研究,我们实现了较高性能的倒装互连,互连条件选择温度在60℃-140℃范围,压力范围0．1克／铟柱-0．5克／铟柱。互连连通率〉99．9％,互连后的芯片组件在低温（77K）与常温（23℃）间不少于100次的反复冲击的情况下,测试接触性能及InSb二极管性能都无变化,满足了互连器件可靠性要求。     

Computational modelling for reliable flip-chip packaging at sub-100 μm pitch using isotropic conductive adhesives

This paper presents the assembly process using next generation electroformed stencils and Isotropic Conductive Adhesives (ICAs) as interconnection material. The utilisation of ICAs in flip-chip assembly process is investigated as an alternative to the lead and lead-free solder alloys and aims to ensure a low temperature (T < 100 °C) assembly process. The paper emphasizes and discusses in details the assembly of a flip-chip package based on copper columns bumped die and substrate with stencil printed ICA deposits at sub-100 μm pitch. A computational modelling approach is undertaken to provide comprehensive results on reliability trends of ICA joints subject to thermal cycling of the flip-chip assembly based on easy to use damage criteria and damage evaluation. Important design parameters in the package are selected and investigated using numerical modelling techniques to provide knowledge and understanding of their impact on the thermo-mechanical behaviour of the flip-chip ICA joints. Sensitivity analysis of the damage in the adhesive material is also carried out. Optimal design rules for enhanced performance and improved thermo-mechanical reliability of ICA assembled flip-chip packages are finally formulated.     

Interconnect resistance characteristics of several flip-chip bumping and assembly techniques

Several flip-chip interconnection methods were compared by measuring interconnect resistance before and after exposure to environments including pre-conditioning, 85°C/85% RH exposure, 150°C storage, and 0–100°C temperature cycling. The goal was to determine an acceptable low-cost, reliable method for bumping and assembling chips to flexible or rigid substrates using flip-chip assembly techniques. Alternative flip-chip bumping methods are compared to a traditional wafer solder bumping method. Flip-chip interconnection methods evaluated included high lead content solder, silver filled conductive adhesive, and gold stud bumps. Under bump metallurgies evaluated included bare aluminum, evaporated Cr/Cr–Cu/Cu, and electroless nickel plating.     

Equivalent circuit model extraction of flip-chip ball interconnects based on direct probing techniques

This letter describes a novel equivalent circuit model extraction approach for flip-chip ball interconnects based on a direct probing techniques. The derived model has been verified up to 40 GHz.     

Chip scale package issues

Availability of board solder joint reliability information is critical to the wider implementation of chip scale packages (CSPs). The JPL-led CSP consortia of enterprises representing government agencies and private companies have joined together to pool in-kind resources for developing the quality and reliability of CSPs for variety of projects. In the process of building the consortia test vehicles, many challenges were identified regarding various aspects of technology implementation. This paper will present our experience in the areas of technology implementation challenges, including design and building both standard and microvia boards, and assembly of two types of CSP test vehicles.     

Packaging using microelectromechanical technologies and planarcomponents

A novel millimeter-wave packaging structure was developed in which a micromachined low-loss planar component and flip-chip devices were integrated on a silicon substrate. A low-loss planar filter was achieved on a 7-mm-square silicon substrate employing an inverted microstrip line and a unique resonator. High attenuation in the stopband was also obtained by introducing a pole control technique. Fabrication of a compact K-band receiver front-end incorporating a built-in filter was realized using multilayered benzocyclobutene (BCB) and flip-chip bonding techniques. Furthermore, we propose an alternative BCB suspended structure and demonstrate a planar antenna for Ka-band applications. These technologies bring to reality high-performance compact packaged systems in millimeter-wave region applications     

Wafer level packaging of a tape flip-chip chip scale packages

The advent of chip scale packages (CSPs) within the semiconductor community has led to the development of wafer scale assembly (WSA) or wafer level packaging (WLP) manufacturing in order to raise assembly efficiencies and lower operating costs. Texas Instruments (TI) has developed a unique WLP process for forming flip-chip, ball grid array packages. The die inputs and outputs of the TI CSP are connected through solder bumps to a polyimide film interposer. Solder balls on the other side of the interposer complete the electrical connection to a customer’s printed circuit board. A wafer-sized array of interposers designed to match the pattern of dies on a wafer is aligned and reflowed to a bumped wafer. The TI WLP process is completed by singulating the CSPs from the wafer using standard wafer saw equipment.Attachment of the interposer to the die as well as applying the die and board level solder bumps are carried out in wafer form using a new bumping technology called Tacky Dots™. Tacky Dots uses an array of sticky dots formed in a photosensitive coating laminated to a polyimide film for transferring and attaching solder spheres to semiconductor substrates. A populated film containing one solder sphere per Tacky Dot is positioned over the wafer or interposer and lowered until the spheres contact the pads. A reflow process transfers the spheres from the film to the wafer or interposer and the film is removed once the spheres have frozen.This paper illustrates the process steps and custom equipment developed for forming the TI CSP. The strategic use of finite element modeling for optimizing the design of the package is outlined. The paper concludes by summarizing the current package level reliability results.     

RoHS检测的样品微波前处理技术研究

本文系统介绍了微波消解和微波辅助萃取在RoHS分析检测中的样品前处理方法.对微波制样的主要影响因素进行了探讨,初步建立最优化的模式程序,获得较好的测定结果.     

Maßnahmen zur Qualitätssicherung in der Flachbaugruppen-Produktion des Elektronikwerk Wien (EWW)

A considerable part of production costs is spent on quality assurance. With a variety of different test methods production steps are controlled. After a rough survey of different production and test methods we focus on non-automated serial processes, which are still influenced by human errors to a certrain degree. A simple micro processor controlled system was developed to make such processes fail safe. Advantages and disadvantages of using such systems in production are reported. Apart from that special attention is paid to repair techniques. In contrast to the above mentioned process repairing is something which is always done by people with special technical education and it is a non monotonous activity. However, one has to face technological problems. An overview of standard repair techniques (assembling and disassembling of integrated circuits like flip-chip, ball grid arrays BGA and chip size packages CSP) is given. Specially laser soldering of BGAs and flip chip is investigated by practical tests and transient thermal simulation.     

A review of sample backside preparation techniques for VLSI

A review of backside sample preparation techniques is presented. These techniques cover mechanical, chemical and other novel approaches such as laser ablation for ceramic and plastic package opening, silicon thinning and silicon polishing. To illustrate the milling process, we present two challenging backside sample preparation examples on a ceramic package and on a TSOP package.     

Ultra-Fine Pitch Stencil Printing for a Low Cost and Low Temperature Flip-Chip Assembly Process

This paper presents the results of a packaging process based on the stencil printing of isotropic conductive adhesives (ICAs) that form the interconnections of flip-chip bonded electronic packages. Ultra-fine pitch (sub-100-mum), low temperature (100degC), and low cost flip-chip assembly is demonstrated. The article details recent advances in electroformed stencil manufacturing that use microengineering techniques to enable stencil fabrication at apertures sizes down to 20mum and pitches as small as 30mum. The current state of the art for stencil printing of ICAs and solder paste is limited between 150-mum and 200-mum pitch. The ICAs-based interconnects considered in this article have been stencil printed successfully down to 50-mum pitch with consistent printing demonstrated at 90-mum pitch size. The structural integrity or the stencil after framing and printing is also investigated through experimentation and computational modeling. The assembly of a flip-chip package based on copper column bumped die and ICA deposits stencil printed at sub-100-mum pitch is described. Computational fluid dynamics modeling of the print performance provides an indicator on the optimum print parameters. Finally, an organic light emitting diode display chip is packaged using this assembly process