Yttrium oxide/silicon dioxide: a new dielectric structure forVLSI/ULSI circuits

Electrical characteristics of Al/yttrium oxide (~260 Å)/silicon dioxide (~40 Å)/Si and Al/yttrium oxide (~260 Å)/Si structures are described. The Al/Y₂O₃/SiO₂/Si (MYOS) and Al/Y₂ O₃/Si (MYS) capacitors show very well-behaved I-V characteristics with leakage current density <10^-10 A/cm² at 5 V. High-frequency C- V and quasistatic C-V characteristics show very little hysteresis for bias ramp rate ranging from 10 to 100 mV/s. The average interface charge density (Q_f+Q _it) is ~6×10¹¹/cm² and interface state density D_it is ~10¹¹ cm^-2-eV^-1 near the middle of the bandgap of silicon. The accumulation capacitance of this dielectric does not show an appreciable frequency dependence for frequencies varying from 10 kHz to 10 MHz. These electrical characteristics and dielectric constant of ~17-20 for yttrium oxide on SiO₂/Si make it a variable dielectric for DRAM storage capacitors and for decoupling capacitors for on-chip and off-chip applications     

High efficiency polycrystalline silicon solar cells using lowtemperature PECVD process

Conventionally directionally solidified (DS) and silicon film (SF) polycrystalline silicon solar cells are fabricated using gettering and low temperature plasma enhanced chemical vapor deposition (PECVD) passivation. Thin layer (~10 nm) of PECVD SiO₂ is used to passivate the emitter of the solar cell, while direct hydrogen rf plasma and PECVD silicon nitride (Si₃N₄) are implemented to provide emitter and bulk passivation. It is found in this work that hydrogen rf plasma can significantly improve the solar cell blue and long wavelength responses when it is performed through a thin layer of PECVD Si₃N₄. High efficiency DS and SF polycrystalline silicon solar cells have been achieved using a simple solar cell process with uniform emitter, Al/POCl₃ gettering, hydrogen rf plasma/PECVD Si₃N₄ and PECVD SiO₂ passivation. On the other hand, a comprehensive experimental study of the characteristics of the PECVD Si₃N₄ layer and its role in improving the efficiency of polycrystalline silicon solar cells is carried out in this paper. For the polycrystalline silicon used in this investigation, it is found that the PECVD Si₃N₄ layer doesn't provide a sufficient cap for the out diffusion of hydrogen at temperatures higher than 500°C. Low temperature (⩽400°C) annealing of the PECVD Si₃N ₄ provides efficient hydrogen bulk passivation, while higher temperature annealing relaxes the deposition induced stress and improves mainly the short wavelength (blue) response of the solar cells     

An Efficient Triple-Tandem Polymer Solar Cell

We present an efficient triple-tandem polymer solar cell with identical poly(3-hexylthiophene) (P3HT) and 1-(3-methoxycarbonyl)-propyl-1-phenyl-(6, 6)C₆₁ (PCBM) bulk heterojunction as the active layers and highly transparent Al (1 nm)/ MoO₃ (15 nm) as the intermediate layer. This intermediate layer is structurally smooth as characterized by atomic force microscopy. Although identical organic active layers are used to construct such triple-tandem cell, a tripled open-circuit voltage of 1.73 V and power conversion efficiency of 2.03% are obtained under simulated solar irradiation of 100 mW/cm² (AM1.5), demonstrating a viable technique for fabricating triple-tandem polymer cell with the intermediate layer of Al/MoO₃.     

Enhancing the Near-Infrared Spectral Response of Silicon Optoelectronic Devices via Up-Conversion

A silicon-based optoelectronic device that exhibits an enhanced response to subbandgap light is described. The device structure consists of a bifacial silicon solar cell with an up- converting (UC) layer attached to the rear. Erbium-doped sodium yttrium fluoride (NaY_0.8F₄ : Er_0.2 ³⁺) phosphors are the optically active centers responsible for the UC luminescence. The unoptimized device is demonstrated to respond effectively to wavelengths (lambda) in the range of 1480-1580 nm with an external quantum efficiency (EQE) of 3.4% occurring at 1523 nm at an illumination intensity of 2.4 W/cm² (EQE = 1.4 times 10^-2 cm²/W). An analysis of the optical losses reveals that the luminescence quantum efficiency (LQE) of the device is 16.7% at 2.4 W/cm² of 1523-nm excitation (LQE = 7.0 times 10^-2 cm²/W), while further potential device improvements indicate that an EQE of 14.0% (5.8 times 10^-2 cm²/W) could be realistically achieved.     

18% efficient silicon photovoltaic devices by rapid thermaldiffusion and oxidation

For the first time, cells formed by rapid thermal processing (RTP) have resulted in 18%-efficient 1 and 4 cm² single-crystal silicon solar cells. Front surface passivation by rapid thermal oxidation (RTO) significantly enhanced the short wavelength response and decreased the effective front surface recombination velocity (including contact effects) from 7.5×10⁵ to about 2×10⁴ ×10⁴ cm/s. This improvement resulted in an increase of about 1% (absolute) in energy conversion efficiency, up to 20 mV in V_ot, and about 1 mA/cm² in J_sc. These RTO-induced enhancements are shown to be consistent with model calculations. Since only 3 to 4 min are required to simultaneously form the phosphorus emitter and aluminum back-surface-field (BSF) and 5 to 6 min are required for growing the RTO, this RTP/RTO process represents the fastest technology for diffusing and oxidizing ⩾18%-efficient solar cells. Both cycles incorporate an in situ anneal lasting about 1.5 min to preserve the minority carrier lifetime of lower quality materials such as dendritic-web and multicrystalline silicon. These high-efficiency cells confirmed that RTP results in equivalent performance to cells fabricated by conventional furnace processing (CFP). Detailed characterization and modeling reveals that because of RTO passivation of the front surface (which reduced J_0c by nearly a factor of ten), these RTP/RTO cells have become base dominated (J_0b≫J_0c), and further improvement in cell efficiency is possible by a reduction in back surface recombination velocity (BSRV). Based upon model calculations, decreasing the BSRV to 200 cm/s is expected to give 20%-efficient RTP/RTO cells     

Ultrathin gate oxide grown on nitrogen-implanted silicon for deepsubmicron CMOS transistors

Nitrogen implantation on the silicon substrate was performed before the gate oxidation at a fixed energy of 30 keV and with the split dose of 1.0×10¹⁴/cm² and 2.0×10¹⁴ /cm². Initial O₂ injection method was applied for gate oxidation. The method is composed of an O₂ injection/N₂ anneal/main oxidation, and the control process is composed of a N₂ anneal/main oxidation. CMOS transistors with gate oxide thickness of 2 nm and channel length of 0.13 μm have been fabricated by use of the method. Compared to the control process, the initial O₂ injection process increases the amount of nitrogen piled up at the Si/SiO₂ interface and suppresses the growth of gate oxide effectively. Using this method, the oxidation retarding effect of nitrogen was enhanced. Driving currents, hot carrier reliability, and time-zero dielectric breakdown (TZDB) characteristics were improved     

Use of porous silicon antireflection coating in multicrystallinesilicon solar cell processing

The latest results on the use of porous silicon (PS) as an antireflection coating (ARC) in simplified processing for multicrystalline silicon solar cells are presented. The optimization of a PS selective emitter formation results in a 14.1% efficiency multicrystalline (5×5 cm²) Si cell with evaporated contacts processed without texturization, surface passivation, or additional ARC deposition. Specific attention is given to the implementation of a PS ARC into an industrially compatible screen-printed solar cell process. Both the chemical and electrochemical PS ARC formation method are used in different solar cell processes, as well as on different multicrystalline silicon materials. Efficiencies between 12.1 and 13.2% are achieved on large-area (up to 164 cm² ) commercial Si solar cells     

Effects of silicon layer properties on device reliability for0.1-μm SOI n-MOSFET design strategies

We employ an advanced simulation method to investigate the effects of silicon layer properties on hot-electron-induced reliability for two 0.1-μm SOI n-MOSFET design strategies. The simulation approach features a Monte Carlo device simulator in conjunction with commercially available process and device simulators. The two channel designs are: 1) a lightly-doped (10¹⁶ cm^-3) channel and 2) a heavily-doped (10¹⁸ cm^-3) channel. For each design, the silicon layer thicknesses (T_Si) of 30, 60, and 90 nm are considered. The devices are biased under low-voltage conditions where the drain voltage is considerably less than the Si/SiO₂ barrier height for electron injection. A comparative analysis of the Monte Carlo simulation results shows that an increase in T_Si results in decreasing hot electron injection into the back oxide in both device designs. However, electron injection into the front oxide exhibits opposite trends of increasing injection for the heavily-doped channel design and decreasing injection for the lightly-doped channel design. These important trends are attributed to highly two-dimensional electric field and current density distributions. Simulations also show that the lightly-doped channel design is about three times more reliable for thick silicon layers. However, as the silicon layer is thinned to 30 nm, the heavily-doped channel design becomes about 10% more reliable instead     

Reduction of oxide charge and interface-trap density in MOScapacitors with ITO gates

The electrical properties of MOS capacitors with an indium tin oxide (ITO) gate are studied in terms of the number density of the fixed oxide charge and of the interface traps N_f and N _it, respectively. Both depend on the deposition conditions of ITO and the subsequent annealing procedures. The fixed oxide charge and the interface-trap density are minimized by depositing at a substrate temperature of 240°C at low power conditions and in an oxygen-rich ambient. Under these conditions, as-deposited ITO films are electrically conductive. The most effective annealing procedure consists of a two-step anneal: a 45-s rapid thermal anneal at 950°C in N₂, followed by a 30 min anneal in N₂/20% H₂ at 450°C. Typical values obtained for N_it and N_f are 4.2×10¹⁰ cm^-2 and 2.8×10¹⁰ cm^-2, respectively. These values are further reduced to 1.9×10¹⁰ cm^-2 and ≲5×10⁹ cm^-2, respectively, by depositing approximately 25 nm polycrystalline silicon on the gate insulation prior to the deposition of ITO     

Effective Work-Function Modulation by Aluminum-Ion Implantation for Metal-Gate Technology (Poly-Si/TiN/SiO2)

The impact of aluminum (Al) implantation into TiN/SiO₂ on the effective work function (EWF) of poly-Si/ TiN/SiO₂ is investigated. Al implanted at 5 keV with a dose of 5 times 10¹⁵ cm^-2 reduces the flatband voltage (V_FB) and the EWF of poly-Si/TiN/SiO₂ stack by ~150 mV compared with the unimplanted poly-Si/TiN/SiO₂ stack. This reduction of V_FB is found to be dose-dependent, which is correlated to the Al concentration at the TiN-SiO₂ interface as evidenced by secondary-ion-mass-spectrometry profiles. The interface dipole created due to the Al presence at the metal-dielectric interface is believed to contribute to the observed V_FB (or EWF) reduction (or increase). This technique for EWF modulation is promising for further threshold-voltage (V_t) tuning without any process complexities and is quite significant for planar and multiple gate field-effect transistors on fully depleted silicon on insulator.     

Silicon solar cells on unidirectionally recrystallized metallurgical silicon

The deposition of a silicon layer containing a p-n junction on a metallurgical silicon substrate has been used for the fabrication of solar cells. The substrate was prepared by the unidirectional solidification of purified metallurgical silicon on a graphite plate, and the active region of the solar cell was deposited by the thermal reduction of trichlorosilane with hydrogen containing appropriate dopants. The current-voltage characteristics of a number of solar cells were measured in the dark and under illumination. The AM1 efficiency of large-area cells (30 cm²) was up to 5.5 percent. When a large-area cell was divided into small-area (5-cm²) ones, the conversion efficiency was found to correlate directly with the dark current-voltage characteristics of, and the structural properties of silicon in, each cell.     

透明叠层结构Ag/MoO_3/Ag阳极对绿光OLED器件性能的影响

本文采用一种结构为Ag/MoO_3/Ag的金属/氧化物/金属(M_1/O/M_2)叠层替代ITO作为OLED器件的阳极,研究Ag/MoO_3/Ag叠层结构变化对于OLED器件电极透过率、亮度、光谱等性能的影响。实验采用真空蒸镀方法制备了一系列器件,器件结构为Ag/MoO_3/Ag/MoO_3(10nm)/NPB(40nm)/Alq_3(60nm)/LiF(1nm)/Al(150nm)。对比器件的电压-电流密度、电压-亮度、光谱特性等数据,表明Ag/MoO_3/Ag的结构为20/20/10(nm)时,器件性能较好。在驱动电压为11V时,其亮度达到18 421cd/m~2,电流效率为2.45cd/A;且因器件中存在微腔效应,其EL光谱蓝移,半高宽变窄。但考虑到530nm处其电极透过率仅为17%,所以经换算该器件实际发光亮度比ITO电极器件更高。该Ag/MoO_3/Ag叠层阳极制作相对简单,经优化后在顶发射和柔性OLED器件方面将具有一定的应用前景。     

A new method of determination of minority carrier diffusion lengthin the base region of silicon solar cells

A new method of determination of the minority carrier diffusion length (L) in the base region of an n⁺-p-p⁺ silicon solar cell using the spectral response of the cell in a middle wavelength (λ) range, e.g., 0.75<λ<0.90 μm is presented. In this method Q_int or if required Q_int/f where Q_int is the internal quantum efficiency of the cell and f=exp(-(x_bα_λ ))(L²α_λ²/L² α_λ²-1), x_b being the distance of base region from the front surface, is plotted against the reciprocal absorption coefficient (α_λ^-1 of silicon. The Q_int versus α_λ ^-1 or else Q_int/f versus α_λ^-1, plot gives an intercept L_MW on the α_λ^-1-axis and a unit intercept on the other axis. The intercept length L_MW is related to L through d/L and S_B, where d is the thickness of the base region and S_B is the back surface recombination velocity of minority carriers. For d/L>2.5, L=L_MW and is independent of S_B. However, for d/L<2.5, the true value of L which may be somewhat different from L_MW can be determined if S_B is known. While most existing long wavelength spectral response (LWSR) methods require d/L to be large (d/L>2.5) is such that tanh(d/L)≈1, this method has no such restriction on d/L. It is highly suitable for cells for which L is large but x_b is small. We have applied the MWSR and LWSR methods to a few n⁺-p-p⁺ silicon solar cells and have found that the former is much superior to the latter if d/L<2.5     

An alternative method for metallization by laser and ion beam irradiation

A scanning Ar⁺ laser beam and a focused 30 keV Ga⁺ ion beam (FIB) have been used to transform an insulating (or high-resistivity semiconducting) noble metal oxide film to a conducting layer. Resulting from these experiments we propose a method for the fast and one-step metallization by laser or ion beam irradiation using platinum oxide thin films, prepared by magnetron sputtering under an argon/oxygen plasma. A maskless patterning of the platinum oxide film is possible by scanned laser and focused ion beam irradiation. Additionally to the scanning methods it is also possible to pattern the PtO₂ film by broad ion beam irradiation using masks. For wiring we patterned conducting areas of up to 2 mm width and up to 15 mm length with a broad Ga⁺ ion beam (energy: 300 keV, dose: 5×10¹⁵ Ga⁺/cm²). The laser- and the ion-patterned large areas could be easily bonded with an Al wire to carry out four-point resistance measurements.     

Lightweight tandem GaAs/CuInSe2 solar cells

High-efficiency, ultralightweight, mechanically stacked 4-cm² thin-film tandem solar cells are discussed. The tandem stack consists of a single-crystal, thin-film Ga(Al)As cell fabricated by the cleavage of lateral epitaxy for transfer (CLEFT) process and adhesively bonded to the top of a CdZnS/CuInSe₂ polycrystalline thin-film cell deposited on glass. Maximum tandem efficiency in a four-terminal configuration of 21.6% AM0 have been demonstrated. This represents the highest thin-film cell efficiency reported to date. Individual subcells with efficiencies of 19.5% for CLEFT GaAs and 3.0% for CuInSe₂ have also been achieved. Cell specific power as high as 600 W/kg has been achieved with a 4-cm² cell weight of 188 mg without coverglass, at an efficiency of 20.8% AM0     

Leakage current comparison between ultra-thin Ta2O5 films and conventional gate dielectrics

Capacitors with ultra-thin (6.0-12.0 nm) CVD Ta₂O₅ film were fabricated on lightly doped Si substrates and their leakage current (I_g-V_g) and capacitance (C-V) characteristics were studied. For the first time, samples with stack equivalent oxide thickness around 2.0 nm were compared with ultra-thin silicon dioxide and silicon oxynitride. The Ta₂O₅ samples showed remarkably lower leakage current, which not only verified the advantages of ultra-thin Ta₂O₅ as dielectrics for high density DRAM's, but also suggested the possibility of its application as the gate dielectric material in MOSFET's     

Transistor characteristics with Ta2O5 gatedielectric

As the gate oxide thickness decreases below 2 nm, the gate leakage current increases dramatically due to direct tunneling current. This large gate leakage current will be an obstacle to reducing gate oxide thickness for the high speed operation of future devices. A MOS transistor with Ta₂O₅ gate dielectric is fabricated and characterized as a possible replacement for MOS transistors with ultra-thin gate silicon dioxide. Mobility, I_d-V_d, I_d-V_g, gate leakage current, and capacitance-voltage (C-V) characteristics of Ta₂O₅ transistors are evaluated and compared with SiO₂ transistors. The gate leakage current is three to five orders smaller for Ta₂O₅ transistors than SiO₂ transistors     

Quality improvement in a-Si films and their application to a-Sisolar cells

A theoretical analysis conducted in order to raise the efficiency of amorphous-silicon (a-Si) solar cells is discussed. Based on the analysis, the quality of the i and p layers was improved. A high-quality a-Si film with a lower impurity concentration and lower defect density than conventional films was fabricated using the super chamber. A reduction in damage to the transparent conductive oxide and an improvement in p and i interface properties was achieved by using a photo-CVD method. This same method was used to study superlattice structure films, to fabricate high-conductivity films with a wider optical bandgap than conventional a-SiC films, and to improve sensitivity in the short-wavelength region. B(CH₃)₃ was used as a p-type doping gas for a-Si film that had a higher quality than that fabricated using B₂H ₆. These technologies made possible a conversion efficiency of 11.7% for 1-cm² single-junction solar cells and a total area conversion efficiency of 9.60% for 100-cm² single-junction integrated-type submodules     

Studies of diffused boron emitters: saturation current, bandgapnarrowing, and surface recombination velocity

The emitter saturation current density, J₀ was measured on diffused boron emitters in silicon for the case in which the emitter surface is passivated by a thermal oxide and for the case in which Al/Si is deposited on the emitter surface. The oxide-passivated emitters have a surface recombination velocity, s, which is near its lowest technologically achievable value. In contrast, the emitters with Al/Si on the surface have surface recombination velocities which approach the maximum possible value of s. From the J ₀ measurements, the apparent bandgap narrowing as a function of boron doping was found. Using this bandgap narrowing data, the surface recombination velocity at the Si/SiO₂ interface was extracted for surface boron concentrations from 3×10¹⁷ to 3×10¹⁹ cm^-3     

Reliable fluorinated thin gate oxides prepared by liquid phasedeposition following rapid thermal process

A reliable fluorinated thin gate oxide prepared by liquid phase deposition (LPD) following rapid thermal oxidation (RTO) in O₂ or nitridation (RTN) in N₂O ambient was reported. Fluorine (F) atoms incorporated into the oxides during LPD process are found to be helpful to the improvement of oxide quality. It is observed that these fluorinated gate oxides show good properties in radiation hardness, charge to breakdown (Q_bd), and oxide breakdown field (E_ox) endurances. Interestingly, the Q_bd 's for the fluorinated gate oxides are 10 times larger than those for the gate oxides prepared by RTO in O₂ or RTN in N₂ O directly. Some of the E_ox's are even higher than 17 MV/cm for the samples investigated in this work