An integrated optical receiver for multilevel data communication over large core step index plastic optical fiber

A BiCMOS integrated optical receiver with high sensitivity and good linearity is presented. An automatic gain control transimpedance amplifier (TIA) and linear post amplifiers are used to maintain a high linearity with multilevel modulation. Using multilevel signaling and large-diameter integrated photodiodes make the presented optical receiver suitable for small-bandwidth high-attenuation large-core PMMA step index plastic optical fiber. A measured sensitivity of −31 dBm (BER = 10⁻⁹) at 250 Mb/s is presented for a binary signal. A data rate of 500 Mb/s and a sensitivity of −25 dBm (BER = 10⁻⁹) are achieved with four-level pulse amplitude modulation (4-PAM). An error-free transmission over 40 m PMMA step index plastic optical fiber was achieved at 500 Mb/s using 4-PAM signaling with the presented multilevel optical receiver.     

DC-Balance Low-Jitter Transmission Code for 4-PAM Signaling

This investigation proposes a novel dc-balanced low-jitter transmission code, a 4-PAM symmetric code, for a 4-PAM signaling system. The 4-PAM symmetric code preserves all of the useful characteristics of the 8B/10B code such as dc-balanced serial data and guaranteed transitions in the symbol stream for clock recovery. Moreover, the proposed method decreases the jitter of the timing transition of the data in the receiver and consumes half of the data bandwidth, because it transmits in 4-PAM. The design results using the UMC 0.18-$mu$m process demonstrate that the new transmission code can decrease the jitter of the transition point by$pm25hbox%$of the transition region. The operation speed of the encoder/decoder for the 4-PAM symmetric code is 819 MHz with 16-b inputs (13.1 Gb/s) and 704 MHz with 16-b outputs (11.3 Gb/s).     

Wide bandwidth low noise pinFET receiver for high-bit-rate opticalpreamplifier applications

A wide bandwidth low noise pinFET receiver has been fabricated and characterised for optical preamplifier applications. The receiver uses a low capacitance planar pin diode as the photodetector. A bandwidth of 7.08 GHz was measured. The measured input noise current for the receiver front-end is lower than 12 pA/√(f). Using a 1.3 μm DFB laser as the transmitter, at a data rate of 4 Gbit/s, the measured receiver sensitivity is -25.5 dBm with a bit-error-rate of 1×10 ^-9. A set of two of such receivers has also been tested in a 1.3 μm polarisation-insensitive optical preamplifier system experiment. The measured receiver sensitivity, including an optical insertion loss of 1.5 dB, is -29.3 dBm     

Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell

A folded multitap transmitter equalizer and multitap receiver equalizer counteract the losses and reflections present in the backplane environment. A flexible 2-PAM/4-PAM clock data recovery circuit uses select transitions for receive clock recovery. Bit-error rate less than 10/sup -15/ and power equal to 40 mW/Gb/s has been measured when operating over a 20-in backplane with two connectors at 10 Gb/s.     

Optical receiver front-end for multilevel signalling

A front-end optical receiver in 0.6 mm BiCMOS technology is introduced to maintain equally spaced levels and constant output signal swing for multilevel signals at different input optical powers. The symbol error rate measurements for 4-PAM signals show a better sensitivity than with a conventional optical receiver. It is believed that this is the first time that complete performance characteristics for an optical receiver front-end designed especially for multilevel data transmission have been reported.     

15 Gbit/s optical receiver using waveguide pin photodiode

The authors report the first optical receiver to use a waveguide pin photodiode as a high-power and high-speed photodiode. Its measured receiver sensitivity of 15 Gbit/s confirms that waveguide pin photodiodes have high-speed potential and flat frequency response under high input powers beyond +10 dBm     

A Robust 4-PAM Signaling Scheme for Inter-Chip Links Using Coding in Space

Increasing demand for high-speed inter-chip interconnects requires faster links that consume less power. Channel coding can be used to lower the required signal-to-noise ratio for a specific bit error rate in a channel. There are numerous codes that can be used to approach the theoretical Shannon limit, which is the maximum information transfer rate of a communication channel for a particular noise level. However, the complexity of these codes prohibits their use in high-speed inter-chip applications. A low-complexity signaling scheme is proposed here. This method can achieve 3–5-dB coding gain over uncoded four-level pulse amplitude modulation (PAM). The receiver for this signaling scheme along with a regular 4-PAM receiver was designed and implemented in a 0.18-$mu$ m standard CMOS technology. Experimental results show that the receiver is functional up to 2.5 Gb/s. This was verified with a bit error rate tester (BERT) and we were able to achieve error free operation at 2.5-Gb/s channel transfer rate. The entire receiver for this scheme consumes 22 mW at 2.5 Gb/s and occupies an area of 0.2 mm $^2$.      

Measurement of excess sensitivity penalty of a four-diodepolarisation diversity coherent receiver

A novel optical polarisation-diversity coherent receiver is described and demonstrated. The receiver optical hybrid consists of three polarising beam splitters and four pin diodes, interconnected with polarisation maintaining fibres. Measurements over arbitrary input polarisations show a receiver sensitivity of -63±0.5 dBm for BER of 10^-9 in a 40 Mbit/s DPSK self-heterodyne system. This receiver sensitivity is within 1±0.5 dB of the sensitivity of a single-channel receiver with matched signal and local oscillator polarisation     

A 0.3-μm CMOS 8-Gb/s 4-PAM serial link transceiver

An 8-Gb/s 0.3-μm CMOS transceiver uses multilevel signaling (4-PAM) and transmit preshaping in combination with receive equalization to reduce intersymbol interference due to channel low-pass effects. High on-chip frequencies are avoided by multiplexing and demultiplexing the data directly at the pads. Timing recovery takes advantage of a novel frequency acquisition scheme and a linear phase-locked loop that achieves a loop bandwidth of 35 MHz, phase margin of 50°, and capture range of 20 MHz without a frequency acquisition aid. The transmitted 8 Gb/s data are successfully detected by the receiver after a 10-m coaxial cable. The 2×2 mm² chip consumes 1.1 W at 8 Gb/s with a 3-V supply     

A variable-frequency parallel I/O interface with adaptivepower-supply regulation

This paper presents a low-power high-speed CMOS signaling interface that operates off of an adaptively regulated supply. A feedback loop adjusts the supply voltage on a chain of inverters until the delay through the chain is equal to half of the input period. This voltage is then distributed to the I/O subsystem through an efficient switching power-supply regulator. Dynamically scaling the supply with respect to frequency leads to a simple and robust design consisting mostly of digital CMOS gates, while enabling maximum energy efficiency. The interface utilizes high-impedance drivers for operation across a wide range of voltages and frequencies, a dual-loop delay-locked loop for accurate timing recovery, and an input receiver whose bandwidth tracks with the I/O frequency to filter out high-frequency noise. Test chips fabricated in a 0.35-μm CMOS technology achieve transfer rates of 0.2-1.0 Gb/s/pin with a regulated supply ranging from 1.3-3.2 V     

A 6 Gbps/pin Low‐Power Half‐Duplex Active Cross‐Coupled LVDS Transceiver with Switched Termination

A novel linear switched termination active cross‐coupled low‐voltage differential signaling (LVDS) transceiver operating at 1.5 GHz clock frequency is presented. On the transmitter side, an active cross‐coupled linear output driver and a switched termination scheme are applied to achieve high speed with low current. On the receiver side, a shared preamplifier scheme is employed to reduce power consumption. The proposed LVDS transceiver implemented in an 80 nm CMOS process is successfully demonstrated to provide a data rate of 6 Gbps/pin, an output data window of 147 ps peak‐to‐peak, and a data swing of 196 mV. The power consumption is measured to be 4.2 mW/pin at 1.2 V.     

A 700-Mb/s/pin CMOS signaling interface using current integratingreceivers

A high speed CMOS signaling interface for application in multiprocessor interconnection networks has been developed. The interface utilizes I-V push-pull drivers, a delay line phase-locked loop (PLL), and sampling of the data on both edges of the clock. In order to increase the noise immunity of the reception, a current-integrating input pin sampler is used to receive the incoming data. Chips fabricated in a 0.8 μm CMOS technology achieve transfer rates of 740 Mb/s/pin operating from a 3.3 V supply with a bit error rate of less than 10^-14     

Characteristics of Gbit/s optical receiver sensitivity and long-span single-mode fiber transmission at 1.3 µm

Sensitivity of a 1.3 μm Ge APD receiver was measured at data rates ranging from 100 Mbits/s to 2 Gbits/s, using a high-speed GaAs FET RZ driver, low-noise Si bipolar transistor (BIT) receiver amplifier, and a highly sensitive TD comparator. The required received optical level at a 10^-9error rate was -31.9 dBm for 2 Gbits/s with a Ge APD/Si BIT front end having a 50 Ω input impedance. A Ge APD/ GaAs FET front end, with a 500 Ω input impedance, brought about 2 dB improvement at 100 Mbits/s, as compared with a Ge APD/Si BIT (50 Ω) front end. A coupling loss of 4 dB, achieved by a hemispherical microlens tipped on a single-mode fiber, and a low fiber loss of 0.57 dB/km, including splice loss, enabled 44.3 km single-mode fiber transmission at 2 Gbits/s. The 1.3 μm transmission system has a data rate repeater-spacing product of 88.6 (Gbit/s)km. Prospects of Gbit/s receiver sensitivity and the 2 Gbit/s transmission system, with more than 50 km repeater spacing, are also discussed.     

High performance 10 Gbit/s pin-FET optical receiver

An optical receiver suitable for a 10 Gbit/s direct detection optical transmission system is described. It uses a pin diode, commercial GaAs MESFETs and hybrid construction techniques on a coplanar substrate. The measured sensitivity of the receiver is -20.4 dBm, which is the best reported sensitivity at 10 Gbit/s for a pin-FET optical receiver to date.<>     

一种用于背板互连的10 Gbit/s接口电路

基于SMIC 40 nm CMOS工艺,提出了一种用于背板互连的10 Gbit/s I/O接口电路。该接口电路由前馈均衡器(FFE)、接收机前端放大器和判决反馈均衡器(DFE)组成。FFE对发射端信号进行预加重,DFE消除较大的残余码间干扰。重点分析了FFE和DFE在消除码间干扰时存在的问题。使用改进的FFE减少对发射端信号的衰减,保证信号到达接收端时具有较大幅度,实现接收机对信号的正确判决,降低系统的误码率。测试结果表明,系统数据率为10 Gbit/s,传输信道在Nyquist频率(即5 GHz)处的衰减为22.4 dB。在1.1 V电源电压下,判决器Slicer输入端信号眼图的眼高为198 mV,眼宽为83 ps。FFE的功耗为31 mW,接收机前端放大器的功耗为1.8 mW,DFE的功耗为5.4 mW。     

Word timing recovery in direct detection optical PPM communicationsystems with avalanche photodiodes using a phase lock loop

A technique for word timing recovery in a direct detection optical pulse position modulation (PPM) communication system is described. It tracks on back-to-back pulse pairs in the received random PPM data sequences with the use of a phase locked loop. The experimental system consisted of an AlGaAs laser diode transmitter (λ=833 nm) and a silicon avalanche photodiode photodetector, and its used Q=4 PPM signaling at a source data rate of 25 Mb/s. The mathematical model developed to characterize system performance is shown to be in good agreement with the experimental measurements. Use of this recovered PPM word clock, along with a slot clock recovery system described previously, caused no measurable penalty in receiver sensitivity when compared to a receiver which used common transmitter/receiver clocks. The completely self-synchronized receiver was capable of acquiring and maintaining both slot and word synchronizations for input optical signal levels as low as 20 average detected photons per information bit. The receiver achieved a bit error probability of 10^-6 at less than 60 average detected photons per information bit     

110-GB/s simultaneous bidirectional transceiver logic synchronizedwith a system clock

A simultaneous bidirectional transceiver logic (SBTL), for a 0.25 μm CMOS embedded array, has a low-voltage-swing input flip-flop circuit and an output flip-flop with a boundary scan to enable a 1.1-Gb/s data transfer per LSI pin with a 550-MHz system clock. Clock skew and jitter minimization enables high bandwidth in a phase-locked system. Measured latency time for transmission is less than 3.0 ns during simultaneous switching mode when the cable length is 18 cm. Average power consumption is 12 mW per pin at 550 MHz. A low-noise output buffer and a controlled collapse chip connection (C4)-based 1595-pin package with on-package capacitors achieve 100-byte data bus. The maximum data bandwidth per LSI is 110 GB/s     

A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL

Three circuit techniques for a 1.5 V, 512 Mb graphic DDR4 (GDDR4) SDRAM using a 90-nm DRAM process have been developed. First, a dual-clock system increases clocking accuracy and expands internal timing margins for harmonious core operation regardless of external clock frequency. Second, a four-phase data input strobe scheme helps to increase the input data valid window. Third, a fully analog delay-locked loop which provides a stable I/O clock and has 31.67 ps peak-to-peak jitter characteristics is designed. On the basis of these circuit techniques, the data rate is 3.2 Gbps/pin, which corresponds to 12.8 Gbps in times32 GDDR4-based I/O. Also, a multidivided architecture consisting of four independent 128 Mb core arrays is designed to reduce power line and output noise.     

Low-noise 8 GHz PIN/FET optical receiver

An ultrawide-bandwidth, low-noise optical receiver has been designed for use in both multigigabit direct-detection or coherent heterodyne systems at 1.3 and 1.55 ?m wavelengths. The receiver consists of a low-capacitance InGaAs PIN photodiode connected to a high-impedance three-stage GaAs FET preamplifier. Inductive peaking at the front end is used to reduce the receiver noise at high frequencies. The receiver has an equivalent input RMS noise current of < 12 pA/?Hz from 4 to 7 GHz. The measured 3 dB bandwidth of 8 GHz is the widest receiver bandwidth reported to date.     

A New Current-Mode Incremental Signaling Scheme With Applications to Gb/s Parallel Links

A new current-mode incremental signaling (CMIS) scheme and a new fully differential current-integrating receiver for high-speed parallel links are presented. The proposed signaling scheme requires only N+1 physical paths for N parallel bits. It possesses the intrinsic advantages of current-mode signaling including high data rates, large signal swing, low switching noise injection, and superior signal integrity. The current-integrating receiver consisting of a transimpedance front-end, an integrator, and a sense amplifier with active inductor shunt peaking offers the key advantages of a low and tunable input impedance for channel termination, large bandwidth, and effective suppression of transient noise coupled to the channels. To assess the effectiveness of the proposed signaling scheme and the current-integrating receiver, a 4-bit parallel link consisting of four bipolar current-mode drivers, five 10-cm microstrip lines with FR4 substrate, and four proposed current-integrating receivers is implemented in UMC 0.13-mum 1.2-V CMOS technology and analyzed using SpectreRF from Cadence Design Systems with BSIM3.3V device models. Simulation results demonstrate that the proposed CMIS scheme and the current-integrating receiver are capable of transmitting parallel data at 2.5GB/s