Compositionally graded interface for passivation of HgCdTe photodiodes

A compositionally graded CdTe-Hg_1−xCd_xTe interface was created by deposition of CdTe on p-HgCdTe and subsequent annealing. The compositionally graded layer between CdTe and HgCdTe was formed by an interdiffusion process and was used for passivation. The composition gradient (Δx) in the interfacial region and the width of the graded region were tailored by adopting a suitable annealing procedure. The effect of process conditions on the interfacial profile and photoelectric properties such as lifetime and surface recombination velocity was studied in detail. Surface recombination velocity of the p-HgCdTe could be reduced to the level of 3,000 cm/s at 77 K, which represents very good passivation characteristics. The passivation layer formed by this method can be used for the fabrication of high performance and stable modern infrared detectors. Thus, a passivation process is developed, which is simple, effective, reproducible, and compatible with the HgCdTe device fabrication and packaging processes.     

MBE原位碲化镉钝化的碲镉汞长波光电二极管列阵

采用分子束外延(MBE)技术在表面生长碲化镉(CdTe)介质膜的p型碲镉汞(HgCdTe)材料,并通过离子注入区的光刻、暴露HgCdTe表面的窗口腐蚀、注入阻挡层硫化锌(ZnS)的生长、形成p-n结的B+注入、注入阻挡层的去除、绝缘介质膜ZnS的生长、金属化和铟柱列阵的制备等工艺,得到了原位CdTe钝化的n+-on-p...     

Bake stability of long-wavelength infrared HgCdTe photodiodes

The bake stability was examined for HgCdTe wafers and photodiodes with CdTe surface passivation deposited by thermal evaporation. Electrical and electrooptical measurements were performed on various long-wavelength infrared HgCdTe photodiodes prior to and after a ten-day vacuum bakeout at 80°C, similar to conditions used for preparation of tactical dewar assemblies. It was found that the bakeout process generated additional defects at the CdTe/ HgCdTe interface and degraded photodiode parameters such as zero bias impedance, dark current, and photocurrent. Annealing at 220°C under a Hg vapor pressure following the CdTe deposition suppressed the interface defect generation process during bakeout and stabilized HgCdTe photodiode performance.     

不同钝化结构的HgCdTe光伏探测器暗电流机制

在同一HgCdTe晶片上制备了单层ZnS钝化和双层（CdTe+ZnS）钝化的两种光伏探测器,对器件的性能进行了测试,发现双层钝化的器件具有较好的性能．通过理论计算,分析了器件的暗电流机制,发现单层钝化具有较高的表面隧道电流．通过高分辨X射线衍射中的倒易点阵技术研究了单双层钝化对HgCdTe外延层晶格完整性的影响,发现单层ZnS钝化的HgCdTe外延层产生了大量缺陷,而这些缺陷正是单层钝化器件具有较高表面隧道电流的原因．     

Investigation of HgCdTe p-n device structures grown by liquid-phase epitaxy

The microstructure of p-n device structures grown by liquid-phase epitaxy (LPE) on CdZnTe substrates has been evaluated using transmission electron microscopy (TEM). The devices consisted of thick (∼21-μm) n-type layers and thin (∼1.6-μm) p-type layers, with final CdTe (∼0.5 μm) passivation layers. Initial observations revealed small defects, both within the n-type layer (doped with 8×10¹⁴/cm³ of In) and also within the p-type layer but at a much reduced level. These defects were not visible, however, in cross-sectional samples prepared by ion milling with the sample held at liquid nitrogen temperature. Only isolated growth defects were observed in samples having low indium doping levels (2×10¹⁴/cm³). The CdTe passivation layers were generally columnar and polycrystalline, and interfaces with the p-type HgCdTe layers were uneven. No obvious structural changes were apparent in the region of the CdTe/HgCdTe interfaces as a result of annealing at 250°C.     

Dependency of p-n junction depth on ion species implanted in HgCdTe

We assessed p-n junction depth and stress in HgCdTe implanted with various ion species. After post-implantation annealing, junction depth was measured using a differential Hall measurement. The stress induced by implantation was determined by measuring wafer curvature or using Raman spectroscopy. Samples with B or Mg implantation had p-n junctions that were three to five times deeper than samples with Ca, Cd, or Hg implantation. The implantation of elements with a small ionic radius, such as B or Mg, leads to compressive stress in implantation layers. In contrast, the implantation of Ca, Cd, or Hg, which are ions with a radius similar to that of Hg cations, leads to a comparatively high tensile stress in the layers. The results indicate that the stress is caused by a change in volume when the implanted ions substitute the Hg sublattice and by an increase in volume caused by the generation of vacancies and interstistials. These results suggest that implantation-induced stress is an important factor influencing the depth of p-n junctions.     

CdTe/ZnS复合钝化层对长波碲镉汞器件性能的影响研究

采用CdTe/ZnS复合钝化技术对长波HgCdTe薄膜进行表面钝化,并对钝化膜生长工艺进行了改进。采用不同钝化工艺分别制备了MIS器件和二极管器件,并进行了SEM、C-V和I-V表征分析,研究了HgCdTe/钝化层之间的界面特性及其对器件性能的影响。结果表明,钝化工艺改进后所生长的CdTe薄膜更为致密且无大的孔洞,CdTe/HgCdTe界面晶格结构有序度获得改善;采用改进的钝化工艺制备的MIS器件C-V测试曲线呈现高频特性,界面固定电荷面密度从改进前的1.671011 cm-2下降至5.691010 cm-2;采用常规钝化工艺制备的二极管器件在较高反向偏压下出现较大的表面沟道漏电流,新工艺制备的器件表面漏电现象获得了有效抑制。     

CdTe钝化的HgCdTe非平衡载流子表面复合速度的实验研究

利用Ａｒ＾＋束央求宙积技术在ＧｇＣｄＴｅ表面实现了低温ＣｄＴｅ介质薄膜的低温生长。在用－ＨｇＣｄＴｅ晶片表面分别用ＣｄＴｅ介质膜、ＨｇＣｄＴｅ自身阳极氧化膜进行表面钝化。利用光电导衰退测量技术测量了两种不同表面钝化的薄ＨｇＣｄＴｅ晶片的非平衡载流子（少数载流子）寿命,并通过光电导衰减信号波形的拟合,得到两种不同表面钝化的ＨｇＣｄＴｅ表面复合速度。实验结果表明,获得的ＣｄＴｅ／ＨｇＣｄＴｅ界面质量已     

多层HgCdTe异质外延材料的热退火应力分析

前期研究采用高温热处理方法,获得了抑制位错的最佳退火条件.通过比对实验,发现不同衬底上HgCdTe表面的CdTe钝化层在热处理过程中对位错的抑制作用各有不同.结合晶格失配应力和热应力对不同异质结构进行理论计算,借助X射线摇摆曲线的倒易空间分析,解释了CdTe钝化层对HgCdTe位错抑制的影响作用.     

HgCdTe钝化过程中形成的镶嵌结构及其热处理效应

通过高分辨X射线衍射仪中的二维点阵研究了溅射的CdTe介质膜对HgCdTe外延层的影响．发现在高溅射能量下沉积的钝化膜由于应力的作用,HgCdTe晶片出现弯曲及大量镶嵌结构,而这种镶嵌结构可通过合理的热处理工艺消除．     

A Study of Sidewall Effects in HgCdTe Photoconductors Passivated with MBE-Grown CdTe

In order to evaluate the effectiveness of CdTe surface passivating layers, HgCdTe photoconductors with and without CdTe sidewall passivation were fabricated. As expected, photoconductors with CdTe sidewall passivation demonstrated significantly higher responsivity in comparison with those without sidewall passivation, indicating the effectiveness of molecular-beam epitaxially (MBE)-grown CdTe as a passivation layer in reducing surface recombination velocity. Characterization of the responsivity differences between photoconductors with and without sidewall CdTe passivation offers a potential method for measuring the interface/surface recombination velocity. This has been demonstrated in this paper by extracting the value of the surface recombination velocity using the Synopsys Sentaurus commercial modeling package to fit experimental responsivity data for fully and partially passivated devices.     

Piezoelectric effects in HgCdTe devices

Piezoelectric effect in long-wavelength infrared (LWIR) HgCdTe has been studied using metal-insulator-semiconductor (MIS) and p-n homojunction devices. A cantilever beam technique was used to measure the shift in flatband voltage in the MIS devices as a function of applied strain, from which piezoelectric constant was derived. This is the first time such a value has been reported in the literature. Subsequent calculation showed that the thermal stress from cryogenic cool (from 300 to 77K) of hybridized infrared devices fabricated on (111) HgCdTe surfaces induced a piezoelectric field of∼1840 V/cm. This field is present in the space charge regions in the semiconductor where there is no free carrier. It reinforces the built-field in an n-on-p diode fabricated on the (111)A HgCdTe surface. Thus, the diode is more prone to the thermal stress than one fabricated on the (lll)B surface. Electrical measurement of reverse-bias dark currents in HgCdTe photodiodes under applied compressive and tensile stress confirmed the existence of a strain-induced field in the junction.     

Characterization of CdTe for HgCdTe surface passivation

The objectives of this work are to study the physical and chemical structure of CdTe films using secondary ion mass spectrometry (SIMS) and atomic force miroscopy (AFM) and to demonstrate the usefulness of these analytical techniques in determining the characteristics of CdTe-passivation films deposited by different techniques on HgCdTe material. Three key aspects of CdTe passivation of HgCdTe are addressed by different analytical tools: a) morphological microstructure of CdTe films examined by atomic force microscopy; b) compositional profile across the interface determined by Matrix (Te)—SIMS technique; c) concentration of various impurities across the CdTe/HgCdTe structure profiled by secondary ion-mass spectrometry.     

Surface Passivation of HgCdTe Using Low-Pressure Chemical Vapor Deposition of CdTe

CdTe passivation films have been deposited on Hg_1?x Cd _x Te (x = 0.35) samples used for infrared detectors by low-pressure chemical vapor deposition (LPCVD) and atomic layer deposition (ALD) at temperatures as low as 135°C to 170°C. ALD has been used to deposit an initially uniform starting surface before continuing the deposition using LPCVD. Favorable conformal coverage has been demonstrated on high-aspect-ratio HgCdTe structures. LPCVD deposition rates of 40 nm/h to 70 nm/h were obtained by varying the sample temperature from 135°C to 170°C. Lifetime measurements carried out at 300 K exhibited a significant improvement in minority-carrier lifetime from 0.9 μs (sample without passivation) to 4.28 μs for samples passivated at 135°C.     

碲镉汞物理与化学钝化界面的AES研究

采用化学和物理方法分别在Hg1-xCdxTe (MCT)表面制备了阳极氟化膜、CdTe、ZnS和类金刚石薄膜(DLC)钝化层.采用俄歇光谱(AES)和红外透射光谱(IR)研究了这些钝化层与MCT之间的界面特性.结果表明与阳极氟化膜和CdTe膜相比,ZnS和DLC膜能较好地抑制MCT组元的外扩散.ZnS层中的Zn和S 易于向MCT内部扩散,而且发现在ZnS层中有O的存在,这可能是由于ZnS易与空气中水份发生作用所致.而DLC中C向MCT内表面扩散较少.MCT表面沉积DLC薄膜后红外透过率较ZnS有明显的提高.     

The interface of metalorganic chemical vapor deposition-CdTe/HgCdTe

The metalorganic chemical vapor deposition (MOCVD) growth of CdTe on bulk n-type HgCdTe is reported and the resulting interfaces are investigated. Metalinsulator-semiconductor test structures are processed and their electrical properties are measured by capacitance-voltage and current-voltage characteristics. The MOCVD CdTe which was developed in this study, exhibits excellent dielectric, insulating, and mechano-chemical properties as well as interface properties, as exhibited by MIS devices where the MOCVD CdTe is the single insulator. Interfaces characterized by slight accumulation and a small or negligible hysteresis, are demonstrated. The passivation properties of CdTe/ HgCdTe heterostructures are predicted by modeling the band diagram of abrupt and graded P-CdTe/n-HgCdTe heterostructures. The analysis includes the effect of valence band offset and interface charges on the surface potentials at abrupt hetero-interface, for typical doping levels of the n-type layers and the MOCVD grown CdTe. In the case of graded heterojunctions, the effect of grading on the band diagram for various doping levels is studied, while taking into consideration a generally accepted valence band offset. The MOCVD CdTe with additional pre and post treatments and anneal form the basis of a photodiode with a new design. The new device architecture is based on a combination of a p-on-n homojunction in a single layer of n-type HgCdTe and the CdTe/HgCdTe heterostructure for passivation.     

Passivation effects on reactive-ion-etch-formed n-on-p junctions in HgCdTe

The formation of n-on-p junctions by reactive ion etching (RIE) of HgCdTe using an H₂/CH₄ plasma has previously been demonstrated to produce high-performance photodiodes. To fully exploit the inherent advantages of this process, a compatible surface-passivation technology that provides long-term stability is required. This paper examines the effects of thermally evaporated CdTe- and ZnS-passivation on RIE-formed photodiodes undergoing low-temperature baking in a vacuum at temperatures typically used for Dewar bakeout. Experimental results show that as a single passivation layer, neither CdTe nor ZnS are suitable for vacuum packaging of RIE-formed diodes that are to be operated at cryogenic temperatures. A double passivation layer, however, consisting of CdTe passivation and an insulating overlayer of ZnS, produces photodiodes that are stable throughout 175 h, approximately 1 week, of 80°C baking in a vacuum.     

Effects of Inductively Coupled Plasma Hydrogen on Long-Wavelength Infrared HgCdTe Photodiodes

Bulk passivation of semiconductors with hydrogen continues to be investigated for its potential to improve device performance. In this work, hydrogen-only inductively coupled plasma (ICP) was used to incorporate hydrogen into long-wavelength infrared HgCdTe photodiodes grown by molecular-beam epitaxy. Fully fabricated devices exposed to ICP showed statistically significant increases in zero-bias impedance values, improved uniformity, and decreased dark currents. HgCdTe photodiodes on Si substrates passivated with amorphous ZnS exhibited reductions in shunt currents, whereas devices on CdZnTe substrates passivated with polycrystalline CdTe exhibited reduced surface leakage, suggesting that hydrogen passivates defects in bulk HgCdTe and in CdTe.     

A CdTe passivation process for long wavelength infrared HgCdTe photo-detectors

Passivant-Hg_1−xCd_xTe interface has been studied for the CdTe and anodic oxide (AO) passivants. The former passivation process yields five times lower surface recombination velocity than the latter process. Temperature dependence of surface recombination velocity of the CdTe/n-HgCdTe and AO/n-HgCdTe interface is analyzed. Activation energy of the surface traps for CdTe and AO-passivated wafers are estimated to be in the range of 7–10 meV. These levels are understood to be arising from Hg vacancies at the HgCdTe surface. Fixed charge density for CdTe/n-HgCdTe interface measured by CV technique is 5×10¹⁰ cm⁻², which is comparable to the epitaxially grown CdTe films. An order of magnitude improvement in responsivity and a factor of 4 increase in specific detectivity (D*) is achieved by CdTe passivation over AO passivation. This study has been conducted on photoconductive detectors to qualify the CdTe passivation process, with an ultimate aim to use it for the passivation of p-on-n and n-on-p HgCdTe photodiodes.     

Electrical and structural properties of epitaxial CdTe/HgCdTe interfaces

In this study, CdTe epilayers were grown by metalorganic chemical vapor deposition on epitaxial HgCdTe with the purpose of developing suitable passivation for HgCdTe photodiodes. Two types of CdTe layers were investigated. One was grown directly,in situ, immediately following the growth of HgCdTe. The second type of CdTe was grown indirectly, on top of previously grown epitaxial HgCdTe samples. In this case, the surface of the HgCdTe was exposed to ambient atmosphere, and a surface cleaning procedure was applied. The material and structural properties of the CdTe/HgCdTe interfaces were investigated using secondary ion mass spectroscopy, Auger electron spectroscopy, Rutherford back scattering, and x-ray double crystal diffractometry techniques. Electrical properties of the CdTe/HgCdTe heterostructure were determined by capacitance-voltage (C-V) characterization of Schottky barrier devices and metal insulator semiconductor devices. Also, a preliminary current-voltage characterization of n⁺ p photodiodes was performed. A theoretical model suitable for analysis of graded heterojunction devices was used for interpretation of C-V measurements.