基板温度对氧化锌薄膜晶体管性能的影响

以ITO玻璃为衬底,利用射频磁控溅射制备了以氧化硅为绝缘层的氧化锌薄膜晶体管。研究了氧化锌薄膜制备过程中不同的衬底温度（衬底温度分别为室温、100℃ 和200℃）对于器件性能的影响。和室温下制备的氧化锌薄膜晶体管相比,衬底温度200℃条件下制备的器件的场效应迁移率提高了94% （从1.6cm2/Vs 提高至3.11cm2/Vs）,亚阈值摆幅 从2.5V/dec 降低至1.9 V/dec 而且阈值电压漂移也从18V 减小至3V （老化电压为25V的正栅压,老化时间为1小时）。实验结果表明,衬底加热对于氧化锌薄膜晶体管的迁移率、亚阈值摆幅和偏压稳定性有明显的影响。利用原子力显微镜AFM对氧化锌薄膜的特性就行了研究,器件性能提高的原因也在文中进行了阐述。     

电致发光器件选址用的高压多晶硅薄膜晶体管

为获得高分辨率和长寿命的电致发光显示板,本文研究了薄膜电致发光器件选址用的高压多晶硅薄膜晶体管(TFT)矩阵。结果,对于32×32点矩阵器件,其源、漏极间的正反向击穿电压都达到100V,并且在0—22V门电压之间的开/关电流比为3×10~3。由于采用激光退火和补偿门结构,制备出交流显示用的高压多晶硅薄膜晶体管,此TFT电路可以驱动电致发光器件。由于多晶硅薄膜被用作薄膜晶体管的半导体,就可应用硅的大规模集成电路工艺来得到高分辨率TFT矩阵,而且不存在化学计量的问题,可以将高质量的热生长氧化物用作门绝缘体。所以,为获得长寿命显示板,已能够制备稳定的硅薄膜晶体管。     

LP-MOCVD法制作n-ZnO/p-Si异质结及其电致发光研究

采用低压-金属有机化学气相沉积法(LP-MOCVD)在(100)p-Si衬底上制备未掺杂n型ZnO薄膜,并制作了相应的n-ZnO/p-Si异质结器件.通过X射线衍射(XRD)、光致发光(PL)光谱和霍尔测试分别研究了所制备薄膜的结构、光学和电学特性.得到具有较高质量的n型ZnO薄膜.在室温条件下,测得了该类异质结器件正向注入电流下可见光和近红外区域的电致发光(EL).     

有机介质层铟锌氧化物薄膜晶体管

利用直流磁控溅射方法在玻璃基板上室温制备非晶铟锌氧化物半导体薄膜,薄膜表面平整。采用旋涂法室温制备聚四乙烯苯酚有机介质层。以铟锌氧化物薄膜作为沟道层、聚四乙烯苯酚作为介质层,成功制备了顶栅结构的薄膜晶体管。测试结果表明,所制备的薄膜晶体管具有饱和特性且为耗尽工作模式,薄膜晶体管的阈值电压为3.8V,迁移率为25.4cm2.V-1.s-1,开关比为106。     

MIC多晶硅薄膜的光学与电学特性及其优化

制备了4种P型掺杂的多晶硅薄膜;固相品化(SPC)、金属诱导(MIC)、准分子激光晶化(ELA)和低压化学气象沉积(LPCVD)多晶硅薄膜,并且研究了它们的光学特性与电学特性.结果发现,MIC多品硅薄膜具有最小的可见光吸收率;ELA和MIC有较小的方块电阻,而SPC和LPCVD方块电阻较大.最后通过对MIC多晶硅薄膜厚度的优化表明,厚度为40 nm的MIC多晶硅薄膜最适合做有机电致发光器件的像素电极.     

采用不同透明电极的非晶铟镓锌氧化物薄膜晶体管

采用透明材料ITO和AZO为源漏电极,在室温下利用射频磁控溅射方法制作了底栅结构的非晶铟镓锌氧化物薄膜晶体管。实验发现,制备的薄膜晶体管均表现出了良好的开关特性。其中采用AZO为电极的薄膜晶体管的场效应迁移率为1.95cm2/V.s,开关比为4.53×105,在正向偏压应力测试下,阈值电压的漂移量为4.49V。     

Ge/SiGe异质结构肖特基源漏MOSFET

制备了氧化铪(HfO2)高k介质栅Si基Ge/SiGe异质结构肖特基源漏场效应晶体管(SB-MOSFET)器件,研究了n型掺杂Si0.16Ge0.84层对器件特性的影响,分析了n型掺杂SiGe层降低器件关态电流的机理。使用UHV CVD沉积系统,采用低温Ge缓冲层技术进行了材料生长,首先在Si衬底上外延Ge缓冲层,随后生长32 nm Si0.16Ge0.84和12 nm Ge,并生长1 nm Si作为钝化层。使用原子力显微镜和X射线衍射对材料形貌和晶体质量进行表征,在源漏区沉积Ni薄膜并退火形成NiGe/Ge肖特基结,制备的p型沟道肖特基源漏MOSFET,其未掺杂Ge/SiGe异质结构MOSFET器件的空穴有效迁移率比相同工艺条件制备的硅器件的高1.5倍,比传统硅器件空穴有效迁移率提高了80%,掺杂器件的空穴有效迁移率与传统硅器件的相当。     

基于不同自组装单层的酞菁氧钒薄膜晶体管

研究了不同界面修饰层对酞菁氧钒(VOPc)薄膜晶体管性能的影响。通过AFM图谱分析不同界面修饰层上VOPc薄膜的生长行为,通过半导体参数测试仪测试分析不同界面上器件的电学特性。实验结果表明,十八烷基三氯硅烷(OTS-18)修饰后生长的VOPc薄膜,比正辛基三氯硅烷(OTS-8)和苯基三氯硅烷(PTS)修饰后的薄膜晶体尺寸更大、质量更优;基于OTS-18修饰的底栅顶接触型VOPc有机薄膜晶体管,在4种结构器件中具有最高的场效应迁移率(0.51cm2/V·s),相对于未修饰的器件迁移率提高了近40倍。较长的烷基链能够有效地隔绝VOPc分子和二氧化硅之间的相互作用,利于形成大晶粒尺寸、少缺陷的优质薄膜,获得高迁移率的TFT器件。绝缘层表面自组装单分子层的厚度对其上薄膜的生长行为和相应器件的性能影响极为明显,这一结论对有机半导体薄膜生长和器件制备具有指导意义。     

铜掺杂氧化锌薄膜的阻变特性

采用脉冲激光沉积法在SnO<,2>:F(FTO)衬底上制备了单一c轴取向生长的ZnO和ZnO:Cu薄膜,并对具有Au/ZnO/FTO和Au/ZnO:Cu/FTO三明治结构的器件进行了阻变特性测试.结果显示:两种器件在室温电场作用下均显示出双极可逆变阻特性;Cu掺杂使ZnO薄膜的开关比大幅增加,电流-电压曲线拟合结果显示...     

薄起始层的VHF PECVD底栅微晶硅薄膜晶体管

对微晶硅薄膜晶体管,尤其对底栅型晶体管,在衬底和晶化层间存在一层非晶相起始层,这将严重影响器件性能.文中采用降低硅烷浓度的方法简便有效地减薄了用超高频化学气相法直接沉积的微晶硅薄膜起始层的厚度,得到起始层厚度小于20nm的微晶硅薄膜.在硅烷浓度为2%的条件下采用四版工艺制备了具有Al/SiNx/μc-Si/n+-μc-Si/Al结构的底栅微晶硅TFT,其开关比(Ion/Ioff)达到106,场效应迁移率为0.7cm2/(V·s),阈值电压为5V左右.     

Active Layer Thickness Effects on the On-State Current and Pulse Measurement at Room Temperature on Deposited Zinc Oxide Thin-Film Transistors

This study reports on the fabrication of thin-film transistors (TFTs) with transparent zinc oxide (ZnO) semiconductors serving as the active channel and silicon dioxide (SiO₂) serving as the gate insulator. The ZnO films were deposited by radiofrequency magnetron sputtering at room temperature. Moreover, the effects of channel thickness on the structural and pulse current?Cvoltage characteristics of ZnO TFTs using a bottom gate configuration were investigated. As the channel thickness increased, the crystalline quality and the channel conductance were enhanced. The electrical characteristics of TFTs exhibited field-effect mobilities of 8.36?cm²/Vs to 16.40?cm²/Vs and on-to-off current ratios of 10⁸ to 10⁷ for ZnO layer thickness of 45?nm and 70?nm, respectively. The threshold voltage was in the range of 10?V to 31?V for ZnO layer thicknesses from 35?nm to 70?nm, respectively. The low deposition and processing temperatures make these TFTs suitable for fabrication on flexible substrates.     

Thermally deposited Ag-doped CdS thin film transistors with high-k rare-earth oxide Nd2O3 as gate dielectric

The performance of thermally deposited CdS thin film transistors doped with Ag has been reported. Ag-doped CdS thin films have been prepared using chemical method. High dielectric constant rare earth oxide Nd₂O₃ has been used as gate insulator. The thin film trasistors are fabricated in coplanar electrode structure on ultrasonically cleaned glass substrates with a channel length of 50 μm. The thin film transistors exhibit a high mobility of 4.3 cm² V^?1 s^?1 and low threshold voltage of 1 V. The ON-OFF ratio of the thin film transistors is found as 10⁵. The TFTs also exhibit good transconductance and gain band-width product of 1.15 × 10^?3 mho and 71 kHz respectively.     

Effect of the deposition rate on the phase transition in silver telluride thin films

Silver telluride thin films of thickness 50 nm have been deposited at different deposition rates on glass substrates at room temperature and at a pressure of 2×10⁻⁵ mbar. The electrical resistivity was measured in the temperature range 300–430 K. The temperature dependence of the electrical resistance of Ag₂Te thin films shows structural phase transition and coexistence of low temperature monoclinic phase and high temperature cubic phase. The effect of deposition rate on the phase transition and the electrical resistivity of silver telluride thin films in relation to carrier concentration and mobility are discussed.     

Investigation of the optical and structural properties of thermally evaporated cadmium sulphide thin films on polyethylene terephthalate substrate

Cadmium sulphide (CdS) thin films of different thicknesses ranging from 100 to 400 nm were prepared on polyethylene terephthalate (PET) substrates at room temperature by thermal evaporation technique in vacuum of about 3×10⁻⁵ Torr. The structural characterisation was carried out by X-ray diffraction (XRD). These studies confirm the proper phase formation of the cadmium sulphide structure. The root mean square (RMS) roughness of the films was measured using atomic-force microscopy. The root mean square roughness of the films increases as the film thickness increases. The energy gap of CdS on PET substrates was determined through the optical transmission method using an ultraviolet–visible spectrophotometer. The optical band gap values of CdS thin films slightly increase as the film thickness increases. The optical band gap energy was found to be in the range of 2.41–2.56 eV.     

Influence of the channel layer thickness on electrical properties of indium zinc oxide thin-film transistor

Thin-film transistors (TFTs) were fabricated on SiO₂/n⁺-Si substrates using amorphous binary In₂O₃-ZnO (a-IZO) films with different thickness for active channel layers deposited by the rf magnetron sputtering at room temperature. The performance of devices was found to be thickness dependent. With the active layer thickness from 33 to 114 nm, the field-effect mobility μ_FE increased from 1.60 to 4.59 cm²/V s, the threshold voltage V_TH decreased from 62.26 to 20.82 V, and the subthreshold voltage swing S decreased from 4.06 V/decade to 1.30 V/decade. Further, the dependence of TFTs’ electrical properties on active layer thickness was investigated in detail on the basis of free carrier density and interface scattering.     

Fabrication of Microstructured thermoelectric Bi2Te3 thin films by seed layer assisted electrodeposition

In this work, bismuth telluride (Bi₂Te₃) thin films have been fabricated on Bi₂Te₃/ITO substrates by constant potential electrochemical deposition at room temperature. Bi₂Te₃ seed layers with different thicknesses (2 nm, 4 nm and 6 nm) were deposited onto ITO substrates using molecular beam epitaxy (MBE) method. The SEM images show that the morphology of Bi₂Te₃ thin films can be controlled not only by the deposition potential, but also the thickness of seed layer. Moreover, the morphologies of Bi₂Te₃ thin films with different thickness of seed layers tend to be similar and contain two-layer structure along the vertical direction after prolonged deposition time. Due to the two layers structure, Bi₂Te₃ thin films have shown different electrical conductivity performances. At room temperature, Bi₂Te₃ thin films with 4 nm-thick seed layer possess the maximum electrical conductivity value of 617.9 s cm^-1.     

氧压对PLD制备掺铜ZnO薄膜光学性质的影响

为了研究生长氧压对ZnO薄膜的结构和光学性质的影响,采用脉冲激光沉积技术,在P-Si〈111〉衬底上制备了不同生长氧压下的掺铜ZnO薄膜.利用X射线衍射仪对样品的结构进行了分析,并用荧光分光光度计对样品的光致发光谱进行了测量.结果表明,所有样品均在2θ=34.3°附近出现ZnO(002)衍射峰,没有发现Cu的衍射峰,在...     

Optical and Dielectric Properties and Microstructures of rf-Magnetron Sputtered ZnO-Doped Zr<Subscript>0.8</Subscript>Sn<Subscript>0.2</Subscript>TiO<Subscript>4</Subscript> Films on Indium Tin Oxide/Glass Substrates

Optical and dielectric properties and microstructures of ZnO-doped (Zr_0.8Sn_0.2)TiO₄ thin films prepared by radiofrequency (rf)-magnetron sputtering on indium tin oxide/glass substrates at different rf powers and substrate temperatures have been investigated. Selected-area diffraction patterns showed that the deposited films exhibited a polycrystalline microstructure. All films exhibited the ZnO-doped (Zr_0.8Sn_0.2)TiO₄ structure with the (111) orientation perpendicular to the substrate surface. The grain size as well as the deposition rate of the film increased with an increase in both rf power and substrate temperature. At an annealing temperature of 700°C, the ZnO-doped (Zr_0.8Sn_0.2)TiO₄ film possessed a dielectric constant of 47 at 10 MHz, a dissipation factor of 0.02 at 10 MHz, a leakage current density of 7.35 × 10⁻⁹  A/cm² at an electrical field of 1 kV/cm, average transmission in the visible range of over 70%, and an optical bandgap of 3.6 eV. This film will allow fabrication of fully transparent semiconductor devices such as a resistive random-access memory (RRAM) and thin-film transistors (TFTs) completely based on ZnO-doped (Zr_0.8Sn_0.2)TiO₄ thin films.     

Post-annealing Effect on Microstructures and Thermoelectric Properties of Bi0.45Sb1.55Te3 Thin Films Deposited by Co-sputtering

p-Type Bi_0.45Sb_1.55Te₃ thermoelectric (TE) thin films have been prepared at room temperature by a magnetron cosputtering process. The effect of postannealing on the microstructure and TE properties of Bi_0.45Sb_1.55Te₃ films has been investigated in the temperature range from room temperature to 350°C. x-Ray diffraction analysis shows that the annealed films have polycrystalline rhombohedral crystal structure, and the average grain size increases from 36?nm to 64?nm with increasing annealing temperature from room temperature to 350°C. Electron probe microanalysis shows that annealing above 250°C can cause Te reevaporation, which induces porous thin films and dramatically affects electrical transport properties of the thin films. TE properties of the films have been investigated at room temperature. The hole concentration shows a trend from descent to ascent and has a minimum value at the annealing temperature of 200°C, while the Seebeck coefficient shows an opposite trend and a maximum value of 245?μV?K^?1. The electrical resistivity monotonically decreases from 19.8?mΩ?cm to 1.4?mΩ?cm with increasing annealing temperature. Correspondingly, a maximum value of power factor, 27.4?μW?K^?2?cm^?1, was obtained at the annealing temperature of 250°C.     

Polycrystalline silicon thin film transistors fabricated in various solid phase crystallized films deposited on glass substrates

In this work, we have characterized various types of polysilicon films, crystallized upon thermal annealing from films deposited by low pressure chemical vapor deposition in the amorphous phase and a mixed phase using silane or in the amorphous phase using disilane. Polysilicon thin film transistors (TFTs) were fabricated, at low processing temperatures, in these three types of films on high strain point Corning Code 1734 and 1735 glass substrates. Double layer films, with the bottom layer deposited in a mixed phase and the top in the amorphous phase, allowed TFT fabrication at a drastically reduced thermal budget; optimum values of thicknesses and deposition rates of the layers are reported for reducing the crystallization time and improving film quality. Optimum deposition conditions for TFT fabrication were also obtained for films deposited using disilane. The grain size distribution for all types of films was shown to be wider for a larger grain size. Fabricated TFTs exhibited field effect electron mobility values in the range of 20 to 50 cm²/V·s, subthreshold swings of about 0.5–1.5 V/dec and threshold voltage values of 2–4 V.