2.7 V 50 MHz IF sampling ΔΣ modulator with +37 dBV IIP3

The design and experimental results of a 2.7 V 50 MHz switched-capacitor DS modulator in a 0.35 μm BiCMOS process are presented. The circuit is targeted for the IF section of a radio receiver in a GSM cellular phone. It combines frequency downconversion with analogue to digital conversion by directly sampling an input signal from an IF of 50 MHz. The measured peak signal-to-noise ratio for a 100 kHz bandwidth is 81 dB with a 53 MHz blocking signal and the measured IIP3 for IF input is +36.9 dBV     

A 1.8-mW CMOS ΣΔ modulator with integrated mixer forA/D conversion of IF signals

In this paper, the design of a continuous-time baseband sigma-delta (ΣΔ) modulator with an integrated mixer for intermediate-frequency (IF) analog-to-digital conversion is presented. This highly linear IF ΣΔ modulator digitizes a GSM channel at intermediate frequencies up to 50 MHz. The sampling rate is not related to the input IF and is 13.0 MHz in this design. Power consumption is 1.8 mW from a 2.5-V supply. Measured dynamic range is 82 dB, and third-order intermodulation distortion is -84 dB for two -6-dBV IF input tones. Two modulators in quadrature configuration provide 200-kHz GSM bandwidth. Active area of a single IF ΣΔ modulator is 0.2 mm² in 0.35-μm CMOS     

A 1.5-V 0.7–2.5-GHz CMOS Quadrature Demodulator for Multiband Direct-Conversion Receivers

An integrated quadrature demodulator with an on-chip frequency divider is reported. The mixer consists of a transconductance stage, a passive current switching stage, and an operational amplifier output stage. A complementary input architecture has been used to increase the transconductance for a given bias current. The circuit is inductorless and is capable of operating over a broad frequency range. The chip was implemented in a 0.13-mum CMOS technology. From 700 MHz to 2.5 GHz, the demodulator achieves 35 dB of conversion voltage gain with 250-kHz IF bandwidth, a double-sideband NF of 10 dB with 9-33 kHz 1/f-noise corner. The measured IIP3 is 4 dBm for a 0.1-MHz IF frequency and 10 dBm for a 1-MHz IF frequency. The total chip draws 20 to 24 mA from a single 1.5-V supply.     

80-MHz bandpass /spl Delta//spl Sigma/ modulators for multimode digital IF receivers

Three fully differential bandpass (BP) /spl Delta//spl Sigma/ modulators are presented. Two double-delay resonators are implemented using only one operational amplifier. The prototype circuits operate at a sampling frequency of 80 MHz. The BP /spl Delta//spl Sigma/ modulators can be used in an intermediate-frequency (IF) receiver to combine frequency downconversion with analog-to-digital conversion by directly sampling an input signal from an IF of 60 MHz to a digital IF of 20 MHz. The measured peak signal-to-noise-plus-distortion ratios are 78 dB for 270 kHz (GSM), 75 dB for 1.25 MHz (IS-95), 69 dB for 1.762 MHz (DECT), and 48 dB for 3.84 MHz (WCDMA/CDMA2000) bandwidths. The circuits are implemented with a 0.35-/spl mu/m CMOS technology and consume 24-38 mW from a 3.0-V supply, depending on the architecture.     

A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC With 100 dB SFDR and 50 fs Jitter

This paper describes a 14-bit, 125 MS/s IF/RF sampling pipelined A/D converter (ADC) that is implemented in a 0.35$muhbox m$BiCMOS process. The ADC has a sample-and-hold circuit that is integrated in the first pipeline stage, which removes the need for a dedicated sample-and-hold amplifier (i.e., “SHA-less”). It also has a sampling buffer that is turned off during the hold clock phases to save power. To accurately estimate and minimize the clock jitter, a new jitter simulation technique was used whose results were verified on silicon. The measured silicon results indicate the highest published IF sampling performance to date and prove the viability of the “SHA-less” architecture for IF/RF sampling ADCs. The ADC is calibration-free and achieves a DNL of less than 0.2 LSB and INL of 0.8 LSB. The SNR is 75 dB below Nyquist, and stays above 71 dB up to 500 MHz. The low-frequency SFDR is about 100 dB, and stays above 90 dB up to about 300 MHz. This is also the first ADC to achieve 14-bit level performance for input signal frequencies up to 500 MHz and to have a total RMS jitter of only 50 fs.     

A Common Source Input Cross Coupled Quad CMOS Mixer*

A CMOS doubly balanced mixer circuit is implemented with a source follower input and a cross coupled mixing quad. The circuit employs an all N-channel configuration and is suitable for high frequency applications. As a down-converter with an RF input of 2.0 GHz and an IF output of 200 MHz, the mixer demonstrates 9 dB of conversion loss with a corresponding input referred third order intercept of 0 dBm. As an up-converter with an IF input frequency of 400 MHz and an RF output of 2.4 GHz, the mixer demonstrates 14 dB of conversion loss.     

IF-sampling fourth-order bandpass /spl Delta//spl Sigma/ modulator for digital receiver applications

Bandpass modulators sampling at high IFs (/spl sim/200 MHz) allow direct sampling of an IF signal, reducing analog hardware, and make it easier to realize completely software-programmable receivers. This paper presents the circuit design of and test results from a continuous-time tunable IF-sampling fourth-order bandpass /spl Delta//spl Sigma/ modulator implemented in InP HBT IC technology for use in a multimode digital receiver application. The bandpass /spl Delta//spl Sigma/ modulator is fabricated in AlInAs-GaInAs heterojunction bipolar technology with a peak unity current gain cutoff frequency (f/sub T/) of 130 GHz and a maximum frequency of oscillation (f/sub MAX/) of 130 GHz. The fourth-order bandpass /spl Delta//spl Sigma/ modulator consists of two bandpass resonators that can be tuned to optimize both wide-band and narrow-band operation. The IF is tunable from 140 to 210 MHz in this /spl Delta//spl Sigma/ modulator for use in multiple platform applications. Operating from /spl plusmn/5-V power supplies, the fabricated fourth-order /spl Delta//spl Sigma/ modulator sampling at 4 GSPS demonstrates stable behavior and achieves a signal-to-(noise + distortion) ratio (SNDR) of 78 dB at 1 MHz BW and 50 dB at 60 MHz BW. The average SNDR performance measured on over 250 parts is 72.5 dB at 1 MHz BW and 47.7 dB at 60 MHz BW.     

A 20 GHz microwave sampler

A microwave sampler circuit which operates over the frequency band of 1-20 GHz and has a number of novel features is described. These features include a wideband microstrip-to-slot balun and a wideband active isolator the function of which is to reduce the local oscillator to RF leakage from the input port of the sampler. The signal-to-noise ratio over the input bandwidth is greater than 20 dB at an input power level of -32 dBm. This signal-to-noise ratio was measured in an IF bandwidth of 175 MHz and includes the contribution from the IF amplifier. The sampler, which is made on alumina using MIC techniques, has an integrated impulse generator driven with a sinusoidal local oscillator of only 20 dBm over the frequency band of 250-350 MHz. The IF signal is in the 10-175-MHz band. The RF input VSWR is better than 2:1 up to 20 GHz, and the oscillator to RF breakthrough is better than -58 dBm (-78 dBc) when driven with a local oscillator of 20 dBm. This unusually low leakage was achieved by using the active isolator prior to the sampling circuit     

A 13.5-mW 185-Msample/s ΔΣ modulator for UMTS/GSMdual-standard IF reception

A system-oriented approach for the design of a UMTS/GSM dual-standard ΔΣ modulator is presented to demonstrate the feasibility of achieving intermediate frequency (IF) around 100 MHz, high dynamic range, and low power consumption at the same time. The circuit prototype implements 78 MHz IF for GSM and 138.24 MHz for wideband code division multiple access (WCDMA), which are set to be 3/4 of the analog-to-digital converter sampling rate. A two-path IF sampling and mixing topology with a low-pass ΔΣ modulator, run at half the sampling rate, is used. Implemented in 0.25-μm CMOS, the circuit achieves dynamic range and peak signal-to-noise and distortion ratio for GSM of 86 and 72 dB, respectively. The corresponding values for WCDMA are 54 and 52 dB, respectively. Optimization is performed at all stages of design to minimize power consumption. The complete circuit consumes less than 11.5 mW for GSM and 13.5 mW for WCDMA at 2.5-V supply, of which 8 mW is due to the analog part     

雷达中频放大器的线性对数双特性设计

雷达数字中频接收机需要一个线性中频预放大电路和一个监测用的对数中频放大器。采用射频变压器形成输入匹配网络,采用高性能低噪声宽带差分放大器AD8350作为线性放大器件,采用双调谐回路作为选频网络,采用魔T电路构成功率分配网络,采用高动态范围宽带对数放大器AD8309作为对数放大器件,设计了一个兼具线性和对数特性的中频放大器。实验表明,该放大器中频输入输出阻抗50Ω,中心频率30 MHz,带宽4 MHz。线性通道增益为18 dB,输出动态范围达98 dB(1 dB压缩点-90 dBm和+8 dBm)。对数通道中,在输入功率为-68 dBm～-8 dBm时,对数放大器输出电压范围对应为0.19 V～2.06 V。     

0.1 THz鳍线单平衡式基波混频电路研究

研究了一种基于石英基片的0.1 THz频段的鳍线单平衡混频电路,混频电路的射频和本振信号分别从WR10标准波导端口通过波导单面鳍线微带过渡和波导微带探针过渡输入,中频信号通过本振中频双工器输出。这是一种新型的混频电路形式,与传统的W波段混频器相比,混频电路可以省略一个复杂的W波段滤波器,具有电路设计简单、安装方便的特点。该电路使用两只肖特基二极管通过倒装焊工艺粘结在厚度为75 m的石英基片上,石英基片相对传统基板,可以极大提高电路加工精度。在固定50 MHz中频信号时,射频90~110 GHz范围内,0.1 THz混频器单边带变频损耗小于9 dB。     

An I/Q mixer with an integrated differential quadrature all-pass filter for on-chip quadrature LO signal generation

A down-conversion in-phase/quadrature (I/Q) mixer employing a folded-type topology, integrated with a passive differential quadrature all-pass filter (D-QAF), in order to realize the final down-conversion stage of a 60 GHz receiver architecture is presented in this work. Instead of employing conventional quadrature generation techniques such as a polyphase filter or a frequency divider for the local oscillator (LO) of the mixer, a passive D-QAF structure is employed. Fabricated in a 65 nm CMOS process, the mixer exhibits a voltage gain of 7-8 dB in an intermediate frequency (IF) band ranging from 10 MHz-1.75 GHz. A fixed LO frequency of 12 GHz is used to down-convert a radio frequency (RF) band of 10.25-13.75 GHz. The mixer displays a third order input referred intercept point (IIP₃) ranging from -8.75 to -7.37 dBm for a fixed IF frequency of 10 MHz and a minimum single-sideband noise figure (SSB-NF) of 11.3 dB. The mixer draws a current of 6 mA from a 1.2 V supply voltage dissipating a power of 7.2 mW.     

Design and implementation of quadrature bandpass sigma-delta modulator used in low-IF RF receiver

This paper presents the design and implementation of quadrature bandpass sigma-delta modulator.A pole movement method for transforming real sigma-delta modulator to a quadrature one is proposed by detailed study of the relationship of noise-shaping center frequency and integrator pole position in sigma-delta modulator.The proposed modulator uses sampling capacitor sharing switched capacitor integrator,and achieves a very small feedback coefficient by a series capacitor network,and those two techniques can dramatically reduce capacitor area.Quantizer output-dependent dummy capacitor load for reference voltage buffer can compensate signal-dependent noise that is caused by load variation.This paper designs a quadrature bandpass Sigma-Delta modulator for 2.4 GHz low IF receivers that achieve 69 dB SNDR at 1 MHz BW and-1 MHz IF with 48 MHz clock.The chip is fabricated with SMIC 0.18 μm CMOS technology,it achieves a total power current of 2.1 mA,and the chip area is 0.48 mm2.     

基于0.35 μm GeSi-BiCMOS工艺的1 GSPS采样保持电路

介绍了一种基于0.35μmGeSi-BiCMOS工艺的1GSPS采样/保持电路。该电路采用全差分开环结构,使用局部反馈提高开环缓冲放大器的线性度;采用增益、失调数字校正电路补偿高频输入信号衰减和工艺匹配误差造成的失调。在1GS/s采样率、484.375MHz输入信号频率、3.3V电源电压下进行仿真。结果显示,电路的SFDR达到75.6dB,THD为-74.9dB,功耗87mW。将该采样/保持电路用于一个8位1GSPSA/D转换器。流片测试结果表明,在1GSPS采样率,240.123MHz和5.123MHz输入信号下,8位A/D转换器的SNR为41.39dB和43.19dB。     

A two-path bandpass ΣΔ modulator for digital IFextraction at 20 MHz

Oversampled bandpass A/D converters based on sigma-delta (ΣΔ) modulation can be used to robustly digitize the types of narrowband intermediate frequency (IF) signals that arise in radios and cellular systems. This paper proposes a two-path architecture for a fourth-order, bandpass modulator that is more tolerant of analog circuit limitations at high sampling speeds than conventional implementations based on the use of switched-capacitor biquadratic filters. An experimental prototype employing the two-path topology has been integrated in a 0.6-μm, single-poly, triple-metal CMOS technology with capacitors synthesized from a stacked metal structure. Two interleaved paths clocked at 40 MHz digitize a 200-kHz bandwidth signal centered at 20 MHz with 75 dB of dynamic range while suppressing the undesired mirror image signal by 42 dB. At low input signal levels, the mixing of spurious tones at DC and f_s/2 with the input appears to degrade the performance of the modulator; out-of-band sinusoidal dither is shown to be an effective means of avoiding this degradation. The experimental modulator dissipates 72 mW from a 3.3 V supply     

一种10位50MHz流水线模数转换器的设计

采用每级1.5 bit和每级2.5 bit相结合的方法设计了一种10位50 MHz流水线模数转换器。通过采用自举开关和增益自举技术的折叠式共源共栅运算放大器,保证了采样保持电路和级电路的性能。该电路采用华润上华(CSMC)0.5μm 5 V CMOS工艺进行版图设计和流片验证,芯片面积为5.5 mm2。测试结果表明:该模数转换器在采样频率为50 MHz,输入信号频率为30 kHz时,信号加谐波失真比(SNDR)为56.5 dB,无杂散动态范围(SFDR)为73.9 dB。输入频率为20 MHz时,信号加谐波失真比为52.1 dB,无杂散动态范围为65.7 dB。     

A high-performance monolithic IF amplifier incorporating electronic gain control

A direct-coupled monolithic IF amplifier that incorporates an active gain control stage and exhibits a power gain of 50 dB and an AGC range of 60 dB at 50 MHz is described. This circuit has negligible change in either input or output admittance, and has excellent signal linearity over the full range of gain control. Experimental and theoretical analyses are made of the large signal response, stability, available gain, and noise behavior of the circuit. An application to color television is discussed in which the functions of the 45-MHz IF amplifier and the dc-AGC circuitry are fabricated on a single die.     

宽带低杂散LFM信号的产生方法与系统设计

针对宽带雷达线性调频信号产生,采用FPGA电路和宽带DAC电路直接产生50 MHz~550 MHz 的线性调频中频信号。将中频信号上变频到2 GHz~2. 5 GHz 的射频频段,再经过2 倍频获得4 GHz~5 GHz的宽频带线性调频信号。为进一步提高射频输出信号的幅度/相位特性,采用幅/相预失真校准方法,并精心设计信号产生系统的中频电路和射频电路,进行了实验研究与分析。对实际系统的测试结果表明,系统产生LFM信号的带外杂散优于-55 dB,带内起伏小于依2 dB,且系统稳定、可靠。     

一种12位50MS/s CMOS流水线A/D转换器

采用TSMC 0.18μm 1P6M工艺设计了一个12位50 MS/s流水线A/D转换器（ADC）。为了减小失真和降低功耗,该ADC利用余量增益放大电路（MDAC）内建的采样保持功能,去掉了传统的前端采样保持电路;采用时间常数匹配技术,保证输入高频信号时,ADC依然能有较好的线性度;利用数字校正电路降低了ADC对比较器失调的敏感性。使用Cadence Spectre对电路进行仿真。结果表明,输入耐奎斯特频率的信号时,电路SNDR达到72.19 dB,SFDR达到88.23 dB。当输入频率为50 MHz的信号时,SFDR依然有80.51 dB。使用1.8 V电源电压供电,在50 MHz采样率下,ADC功耗为128 mW。     

10 GHz dual-conversion low-IF downconverter with microwave and analogue quadrature generators

A 10 GHz dual-conversion low-IF downconverter using 0.18-mum CMOS technology is demonstrated. The high-frequency quadrature RF and LO₁ signals are generated by broadside-coupled quadrature couplers while a two-section polyphase filter is utilised for the low-frequency LO₂ quadrature signal generation. As a result, the demonstrated downconverter achieves a conversion gain of 7 dB, IP_{1 dB} of -16 dBm, IIP₃ of -5 dBm and noise figure of 26 dB at a 1.8 V supply. The image-rejection ratio of the first/second image signal is 33/42 dB for IF frequency ranging from 10 to 60 MHz, respectively.