A 3.16–7 GHz transformer-based dual-band CMOS VCO

A dual-band, wide tuning range voltage-controlled oscillator that uses transformer-based fourth-order(LC) resonator with a compact common-centric layout is presented. Compared with the traditional wide band(VCO), it can double frequency tuning range without degrading phase noise performance. The relationship between the coupling coefficient of the transformer, selection of frequency bands, and the quality factor at each band is investigated. The transformer used in the resonator is a circular asymmetric concentric topology. Compared with conventional octagon spirals, the proposed circular asymmetric concentric transformer results in a higher qualityfactor, and hence a lower oscillator phase noise. The VCO is designed and fabricated in a 0.18- m CMOS technology and has 75% wide tuning range of 3.16–7.01 GHz. Depending on the oscillation frequency, the VCO current consumption is adjusted from 4.9 to 6.3 m A. The measured phase noises at 1 MHz offset from carrier frequencies of 3.1, 4.5, 5.1, and 6.6 GHz are –122.5, –113.3, –110.1, and –116.8 d Bc/Hz, respectively. The chip area, including the pads, is 1.20.62 mm2 and the supply voltage is 1.8 V.     

锁相环频率综合器中高性能电荷泵设计

本文基于0.18μm CMOS工艺设计并实现了一种新的高性能电荷泵电路。采用宽输入范围的轨到轨运算放大器和自偏置共源共栅电流镜技术提高了电荷泵在宽输出电压范围内的电流匹配精度;同时,提出通过增加预充电电流源技术来提高电荷泵的初始充电电流,以缩短CPPLLs的建立时间。测试结果表明电荷泵在0.4～1.7V输出电压范围内失配电流小于0.4%,充电电流为100μA,预充电电流为70μA。在1.8V电源电压下,电荷泵电路锁定时的平均功耗为0.9mW。     

一款采用跨导增强技术的新型宽带低噪声放大器

A new broadband low-noise amplifier （LNA） is proposed. The conventional common gate （CG） LNA exhibits a relatively high noise figure, so active gin-boosting technology is utilized to restrain the noise generated by the input transistors and reduce the noise figure. Theory, simulation and measurement are shown. An implemented prototype using 0.13 μm CMOS technology is evaluated using on-wafer probing. S11 and S22 are below -10 dB across 0.1-5 GHz. Measurements also show a gain of 18.3 dB with a 3 dB bandwidth from 100 MHz to 2.1 GHz and an ⅡP3 of-7 dBm at 2 GHz. The measured noise figure is better than 2.5 dB below 2.1 GHz, is better than 4.5 dB below 5 GHz, and at 500 MHz, it gets its minimum value 1.8 dB. The LNA consumes 9 mA from 1.5 V supply and occupies an area of 0.04 mm^2.     

CMOS毫米波低功耗超宽带共栅低噪声放大器

陈述了一个基于单端共栅与共源共栅级联结构的超宽带低噪声放大器(LNA).该LNA用标准90-nm RFCMOS工艺实现并具有如下特征:在28.5～39 GHz频段内测得的平坦增益大于10 dB;-3 dB带宽从27～42 GHz达到了15 GHz,这几乎覆盖了整个Ka带;最小噪声系数(NF)为4.2dB,平均NF在27 ～ 42 GHz频段内为5.1 dB;S11在整个测试频段内小于-11 dB.40 GHz处输入三阶交调点(IIP3)的测试值为+2 dBm.整个电路的直流功耗为5.3 mW.包括焊盘在内的芯片面积为0.58 mm×0.48 mm.     

一种应用于深亚微米CMOS工艺的ESD保护电路

本文研究了一种基于动态栅极悬浮技术的ESD保护电路,并根据全芯片ESD防护的要求设计了试验电路。采用TSMC 0.18μm CMOS工艺实现了试验电路,测试显示芯片的ESD失效电压达到了7kV。     

40Gb/s 0.18μm CMOS甚短距离并行光接收前端放大器

研制成功一种应用于甚短距离(VSR)光传输系统的40Gb/s 并行光接收前端放大器芯片.该电路采用12路并行信道结构和0.18μm CMOS工艺,单信道传输速率达到了3.318Gb/s.电路设计采用了RGC结构和噪声优化技术,克服了CMOS光检测器大寄生电容造成的带宽不够的问题.提出了一种同时采用P 保护环(PGR)、N 保护环(NGR)和深N阱(DNW)的并行放大器隔离结构,有效地抑制了并行放大器之间的串扰,减小了放大器之间的衬底耦合噪声.测试表明,所有信道在3.318Gb/s数据速率、2mVpp输入和2pF的寄生电容下均得到了清晰的眼图.芯片采用1.8V电源供电,单路前端放大器的功耗为85mW,12路总功耗约为1W.     

无线局域网接收机用频率综合器的关键技术

对无线局域网接收机用锁相环型频率综合器的几项关键技术进行了研究.首先分析了锁相环型频率综合器的结构并提出了系统的主要参数.采用TSMC 0.18μm射频CMOS工艺设计了一个具有低相位噪声的单片LC调谐型压控振荡器.其在4.189GHz频点上4MHz频偏处所测得的相位噪声为-117dBc/Hz.采用TSMC 0.18μm混合信号CMOS工艺实现了具有低功耗的下变频模块电路.该电路在1.8V电源供电下可正常工作,功耗为13mW.     

5GHz0．18μm CMOS功率放大器设计

文中介绍了一个基于TSMC 0．18μm CMOS工艺,可应用于802．11a无线局域网标准的功率放大器设计。该电路采用三级全差分结构,驱动级采用电阻并联负反馈网络来保证稳定性。在3．3V电源电压下,增益为16dB,输出1dB压缩点为17dBm,电路功耗为0．8 W,效率为18．1%。芯片面积为1．2mm×1．1 mm。     

宽带CMOS低噪声放大器的设计

文章主要介绍应用于集群接收机系统的350MHz～470MHz低噪声放大器,采用0.6μm CMOS工艺。探讨了优化低噪声放大器的噪声系数、增益与线性度的设计方法,同时对宽带输入输出匹配进行了分析。这种宽带低噪声放大器的工作带宽350MHz～470MHz,噪声系数小于3dB,增益为24dB,增益平坦度为±1dB,输入1dB压缩点大于-15dBm。