吸除二次缺陷改善器件参数

本文采用予氧化吸除法和慢速升降温法,吸除工艺中引进的二次缺陷,改善二极管电学参数,提高MOS电容的弛豫时间。 为探讨二次缺陷对MOS器件性能的影响,制作面积为4×10~(-4)厘米~2的二极管阵列和MOS电容器。比较了同一硅片上吸除部分和未吸除部分的二极管漏电,Ⅰ-Ⅴ特性和MOS电容弛予时间。测量偏压为20伏特,规定I_(DS)<100PA的管芯为合格管芯。未吸除部分二极管的平均成品率的16％,经氮化硅吸除部分的成品率增到79％。经磷吸除再加上慢速升降温过程,二极管的平均成品率为94％。吸除改进了二极管的Ⅰ-Ⅴ特性,给出二极管面积上的层错个数与Ⅰ-Ⅴ特性的关系。吸除使MOS电容器的弛予时间提高了两个数量级以上。     

用MOS电容瞬态电流-电容法直接测定少数载流子的体产生寿命分布和表面产生速度

本文提出了一种灵敏方便的MOS电容瞬态电流-电容法,即I-C法,应用它可直接从MOS电容相关的瞬态电流I-t和瞬态电容C-t曲线方便地测定出耗尽层中少数载流子的体产生寿命分布τ_g(x_d)和表面产生速度S_g等参数.文中导出和分析了MOS结构较普遍的瞬态电荷、电流和电容方程,以及界面态密度N_(ss)(E_s)、寿命τ_g(x_d)和(τ|-)_g(x_d)、S_g的计算公式.从τ_g分布的测定结果可见,MOS结构中在约3μm宽的界面层内,从体内向界面τ_g明显下降.     

离子注入层少子寿命空间分布的测量

本文分析了非均匀掺杂衬底MOS电容对线性扫描电压的瞬态响应,提出了饱和电容法测量非均匀掺杂MOS电容少子产生寿命空间分布的方法.该方法的优点是测量与计算简单.     

薄栅介质陷阱密度的求解和相关参数的提取

采用恒定电流应力对薄栅氧化层MOS电容进行了TDDB评价实验,提出了精确测量和表征陷阱密度及累积失效率的方法.该方法根据电荷陷落的动态平衡方程,测量恒流应力下MOS电容的栅电压变化曲线和应力前后的高频C-V曲线变化求解陷阱密度.从实验中可以直接提取表征陷阱的动态参数.在此基础上,可以对器件的累积失效率进行精确的评估.     

薄栅介质陷阱密度的求解和相关参数的提取

采用恒定电流应力对薄栅氧化层MOS电容进行了TDDB评价实验,提出了精确测量和表征陷阱密度及累积失效率的方法.该方法根据电荷陷落的动态平衡方程,测量恒流应力下MOS电容的栅电压变化曲线和应力前后的高频C-V曲线变化求解陷阱密度.从实验中可以直接提取表征陷阱的动态参数.在此基础上,可以对器件的累积失效率进行精确的评估.     

高温恒定电场栅氧化层TDDB寿命测试方法研究

介绍了薄栅氧化层TDDB可靠性评价的高温恒定电场试验方法,并完成了E模型的参数提取,同时以MOS电容栅电流Ig为失效判据。对某工艺的MOS电容栅氧化层TDDB寿命进行了评价。该试验方法解决了在高温条件下对工作器件进行可靠性评价的问题,方法简便可靠,适用于亚微米和深亚微米工艺线的可靠性评价。     

全硅化物金属栅MOS电容的C-V测量技术研究

本文研究了薄栅氧MOS电容C-V特性测量方法和电容模型的适用性。当氧化层漏电较大时,采用二元并联或二元串联简单模型不能准确测量得到MOS电容真实值,需采用并联电导和串联电阻的三元模型或进一步考虑串联电感的四元模型,进行双频率测试。本文在Ni全硅化物（FUSI）金属栅MOS结构上用双频率技术分别采用三元和四元模型进行了测量,结果表明,三元模型测量得到MOS电容仍具有一定的频率依赖性,而采用四元模型得到的MOS电容几乎没有频率依赖性,即更接近于真实值。本文还分析和试验了Ni FUSI栅MOS电容的面积对测试准确度的影响。结果表明,减小MOS电容的面积,可以有效地减小电容模型损耗因子,提高测量准确度,电容频率依赖性降低,在一定条件下,采用简单二元串联模型就可以得到可靠的C-V特性曲线。用考虑量子效应修正的NCSU C-V计算软件分析获得的电容值可计算出栅介质厚度。另外,本文研究了超薄栅氧上Ni FUSI栅MOS电容的准静态C-V测试和光照高频C-V测试。结果表明,对于超薄栅氧由于其漏电增大,其漏电流已明显干扰准静态C-V测试中的位移电流,严重影响电容测试的准确性;而采用光照高频C-V可避免漏电流的影响,较准确地测得MOS电容的低频C-V特性,为全硅化反应完成与否提供判断依据,为研究SiO2/Si界面态特性提供工具和手段。     

SiC掺氯热氧化技术与SiC MOS电容偏压温度不稳定性

偏压温度不稳定性(BTI)是影响SiC MOS器件性能的关键因素。提出了一种制备SiC MOS电容的新工艺，即在SiC干氧氧化气氛中掺入氯化氢(HCl),并对比了不同HCl与O₂体积流量比对SiC MOS电容电学性能的影响。结果表明，该工艺有效地改善了SiC MOS电容的栅氧击穿特性，降低了界面态密度，提升了平带电压稳定性。二次离子质谱(SIMS)和X射线光电子能谱(XPS)测试分析表明，掺氯热氧化技术能够有效消除界面缺陷。进一步分析表明，SiC掺氯热氧化技术能够降低可动离子面密度和氧化层陷阱电荷密度，能够有效改善器件的BTI特性。     

V-MOS功率晶体管反馈电容和输入电容的测量

源极跟随器在高跨导、大负载电阻时,其输入电容近于MOS晶体管反馈电容,本文提出了利用此原理测试MOS管反馈电容和输入电容的方法。与利用密勒积分效应测量反馈电容等方法比较,本方法具有测量简便、准确的优点,尤其是适于在MOS晶体管生产中电容参数的测量。     

用线性电压扫描的电容-时间瞬态测定少子产生寿命

本文建议用耗尽的线性扫描电压扫描MOS电容样品。扫描开始前MOS电容被置于强反型态,以消除表面产生的影响。根据扫描所得的电容-时间瞬态曲线,可确定样品中少于产生寿命。实验表明,对于同一个MOS电容样品,不同电压扫描率下得到的结果有很好的一致性,且与饱和电容法的结果相符合。     

Effective lifetimes in high quality silicon devices

A correct interpretation of pn junction current-voltage and pulsed MOS capacitance-time data allows space-charge region width dependent generation parameters to be separated from bulk controlled recombination parameters. This is very important for the correct extraction of generation lifetime and minority carrier diffusion length, especially for intrinsically gettered devices where the recombination center density varies through the device. Methods to do this are discussed in this paper.     

Measurement of the minority-carrier lifetime using an MOS capacitor

A simple technique is described for the measurement of the minority-carrier recombination lifetime using an MOS capacitor operating as a charge injection device. Device lag resulting from the incompleteness of the charge injection process is measured as a function of the injection pulse width. An approximate diffusion model consisting of only one adjustable parameter, the recombination lifetime, is able to explain the observed lag data. The values of the recombination lifetime thus obtained are in good agreement with those measured by photoconductive decay for a variety of Si samples. This technique permits a more definitive measurement of the minority-carder lifetime in fabricated devices than presently used procedures, without requiring high-quality devices. This technique should be particularly useful for evaluating III-V and II-VI compound semiconductors because MOS capacitors with a low density of interface states often are not available.     

Electrical parameters degradation law of MOSFET during ageing

A new method to extract the different electrical parameters lifetime of MOS transistors submitted to hot carriers degradation is proposed. This method leads to error on the lifetime below 15%, even if the parameter variation measurement reaches only 8%. The robustness of this method has been tested for various biases of stress and different technologies representative of different ageing mechanisms. Finally this method is a good indicator of the degradation modes occurring during the stress.     

Determining the generation lifetime in a MOS capacitor using linear sweep techniques

A comparison between two linear sweep techniques for generation lifetime profiling is reviewed here. These semiconductor characterization techniques find widespread application because of their availability in commercial equipment and ability to reduce the measurement time. It is shown experimentally that parameters such as generation lifetime and surface generation velocity determined by linear sweep techniques agree well with those obtained from pulsed MOS capacitor measurement.     

Characterization of leakage currents in long-lifetime capacitors

The purpose of this paper is to present a new procedure that yields the material parameters characterizing leakage currents in MOS devices (generation lifetime in the depletion region τg, recombination lifetime in the bulk τr, interfacial generation velocity S) by means of the linear-sweep technique at different temperatures and at different depths of the depletion region. This characterization method is applied to long-lifetime MOS capacitors for which different contributions to the leakage current (generation in the depletion region, diffusion from the neutral bulk and interfacial generation) are of the same order of magnitude.     

Czochralski-grown nitrogen-doped silicon: Electrical properties of MOS structures; A positron annihilation study

Czochralski-grown nitrogen-doped (NCZ) silicon was studied using different methods. Measurements of interface traps density, effective generation lifetime and effective surface generation velocity were performed on selected Metal-Oxide-Semiconductor (MOS) structures. Application of the positron annihilation technique (PAS)—pulsed low energy positron system (PLEPS)—was focused on the detection of nitrogen-related defects in NCZ silicon in the near surface region. PAS—PLEPS technique gave relevant results on p-type NCZ silicon. Low sensitivity in the application to n-type NCZ silicon discriminates the PAS—PLEPS technique and should be alternated by other experimental technique. On the other hand, more pertinent measurement of generation lifetime was performed on MOS structures with n-type Si. Although the generation lifetime decreases in NCZ silicon, considerable lateral homogenization of the relaxation time was observed on the wafer.     

Majority- and minority-carrier lifetime in MOS structures

The technique proposed by Goetzberger and Nicollian to determine carrier lifetime in MOS structures from admittance measurements in inversion, is reexamined. The interpretation of the experimental results is carried out in terms of a simplified equivalent circuit, which is topologically the same as that used by the preceding Authors, but differs for the expressions of some parameters appearing in it. The validity of the above equivalent circuit in inversion is demonstrated by comparing the frequency dependence of its admittance, both with the transmission line model, and with experimental results.

Majority and minority carrier lifetime measurements are performed on n-type 100 and 111 oriented samples, oxidized both in the presence and in the absence of hydrochloric acid. It is shown that the addition of HCl to the oxygen-gas stream has determined a three-fold increase in the majority-carrier lifetime, and a sixty-fold one in the minority-carrier lifetime. The latter observation would indicate that HCl acts on the SRH centers by modifying their capture-cross section, rather than rendering them electrically inactive as assumed in earlier papers.     

脉冲MOS结构少子产生寿命的统一表征

本文提出了一种采用脉冲ＭＯＳ结构测量少子产生寿命的统一表征谱方法，此方法基于任何一种收敛弛豫过程均可以转换成一种衰减的指数函数的思想，应用关以样原理获得脉冲ＭＯＳ结构瞬态电容差值谱，从谱图中我们可以直接得到关于少子产生寿命信息。本文综合了众多脉冲ＭＯＳ结构测量少子产生寿命的物理模型，分析了不同模型之间的精细差别。     

Physical characterization of deep bulk levels by the MOS conductance technique

The a.c. response of SRH centers in the bulk silicon of an MOS capacitor is reconsidered in the case of traps far from midgap for which the dominant dissipative process is the a.c. delay in capture and emission of majority carriers. Following the Nicollian and Goetzberger's scheme the MOS admittance is calculated in the whole range of biases starting from a model equivalent circuit in which minority carriers are supposed to be disconnected from the bulk. Henceforth the conductance technique can be employed to characterize the deep bulk levels not only in strong inversion, as previously done by others Authors, but also in the depletion-weak inversion mode. This extension is accomplished without the need of extensive numerical computation and makes it possible to obtain from measurements performed at room temperature the physical parameters of the SRH centers, including their energy level and, in principle, their degeneracy factor.Results of measurements performed on 〈1, 0, 0〉-oriented, CZ and FZ grown wafers are presented. Good correlation is obtained between theory and experiment for the trap conductance as a function of frequency at different values of the surface potential. The deduced density of SRH centers and energy level are also confirmed by DLTS and transient current measurements. Finally, evidence is reported for the existence of a two level trap, probably related to oxygen, in commercial CZ wafers.