HIST: A hierarchical self test methodology for chips,boards, and systems

This article presents the HIST approach, which allows the automated insertion of self test hardware into hierarchically designed circuits and systems to implement the RUNBIST instruction of the IEEE 1149.1 standard. To achieve an optimal and throughout self testable system, the inherent design hierarchy is fully exploited. All chips and boards are provided with appropriate test controllers at each hierarchy level. The approach is able to detect all those faults, which are in the scope of the underlying self test algorithms. In this paper the hierarchical test architecture, the test controllers as well as all necessary synthesis procedures are presented. Finally a successful application of the HIST approach to a cryptography processor is described.     

Synthesis of Native Mode Self-Test Programs

Recent studies show that at-speed functional tests are better for finding realistic defects than tests executed at lower speeds. This advantage has led to growing interest in design for at-speed tests. In addition, time-to-market requirements dictate development of tests early in the design process. In this paper, we present a new methodology for synthesis of at-speed self-test programs for microprocessors. Based on information about the instruction set, this high-level test generation methodology can generate instruction sequences that exercise all the functional capabilities of complex processors. Modern processors have large memory modules, register files and powerful ALUs with comprehensive operations, which can be used to generate and control built-in tests and to evaluate the response of the tests. Our method exploits the functional units to compress and check the test response at chip internal speeds. No hardware test pattern generators or signature analyzers are needed, and the method reduces area overhead and performance impact as compared to current BIST techniques. A novel test instruction insertion technique is introduced to activate the control/status inputs and internal modules related to them. The new methodology has been applied to an example processor much more complex than any benchmark circuit used in academia today. The results show that our approach is very effective in achieving high fault coverage and automation in at-speed self-test generation for microprocessor-like circuits.     

单片机创新实验板系统的设计与应用

传统教学用实验箱缺少培养学生独立设计硬件的环节,偏重软件设计,学生动手能力和创新性不足。为此,引入了模块化思想,将系统按功能分成6个模块,设计了创新实验板系统,采用串口通信原理,实现宿主计算机和单片机之间的通信问题。该系统要求学生根据需求,自主选材、独立设计并焊接实验板,编程之前需要自己设计实验方案并进行连线。该系统使学生参与从硬件设计到软件实现的单片机应用系统开发的全部过程,有效地弥补传统实验箱在硬件教学上的不足,全程培养学生动手能力和解决问题的能力。结果表明,本系统具有很好的稳定性和灵活性。     

Functional Validation of Mixed Hardware/Software Systems based on Specification, Partitioning, and Simulation of Test Cases

Tecs is a test case development methodology for the functional validation of large electronic systems, typically consisting of several custom hardware and software components. The methodology determines a hierarchical top-down test case development process including test case specification, validation, partitioning and implementation. The test case development process addresses the functional validation of the system and its components such as ASICs, boards, HW and software modules; it does not facilitate timing or performance verification. The system functions are used to define test cases at the system level and to derive sub-functions for the system components. Test cases are specified, using a special purpose formalism, and validated before they are applied to the system under test. Furthermore, we propose a technique to partition test cases corresponding to the partitioning of the system into sub-systems and components. This technique can significantly reduce system simulation time because it allows the full validation of system functions by simulation at the sub-system and component level. The system model need only be simulated with a reduced set of stimuli to validate the interfaces between sub-systems. We present a test case specification language and tools that support the proposed methodology. The validation of a switching function illustrates methodology, language, and tools.     

一种SoC片上调试与可测性的整合设计

随着SoC的复杂度和规模的不断增长,SoC的片上调试与可测性变得越来越困难和重要。片上调试与可测性都是系统芯片设计的重要组成部分。文章针对某款32位SoC,充分利用CPU核原有的调试结构,提出一种可测试系统与调试系统的一体化结构设计,并针对不同的模块利用不同的测试策略。基于JTAG端口,该结构能够进行系统程序的调试、边界扫描的测试、扫描链的测试、嵌入式SRAM的内建自测试,同时有效地降低了电路逻辑规模,实现了在测试覆盖率和测试代价之间的一个有效折衷。     

一种基于DSP的并行信号处理系统的设计

讨论了一种并行信号处理系统，该系统采用高性能的并行DSP芯片作为处理单元，构成了分布式的并行结构，具有很强的可扩充性和灵活性。算法软件和数据传输软件的标准模块用汇编语言完成，以达到高效地实时处理；主程序用高级语言设计，可以方便地调用各标准软件模块，整个程序具备易修改、易维护的特点。     

A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores

We have introduced a low-cost at-speed BIST architecture that enables conventional microprocessors and DSP cores to test their functional blocks and embedded SRAMs in system-on-a-chip architectures using their existing hardware and software resources. To accommodate our proposed new test methodology, minor modifications should be applied to base processor within its test phase. That is, we modify the controller to interpret some of the instructions differently only within the initial test mode. In this paper, we have proposed a fuctional self-test methodology that is deterministic in nature. In our proposed architecture, a self test program called BIST Program is stored in an embedded ROM as a vehicle for applying tests. We first start with testing processor core using our proposed architedture. Once the testing of the processor core is completed, this core is used to test the embedded SRAMs. A test algorithm which utilizes a mixture of existing memory testing techniques and covers all important memory faults is presented in this paper. The proposed memory test algorithm covers 100% of the faults under the fault model plus a data retention test. The hardware overhead in the proposed architecture is shown to be negligible. This architecture is implemented on UTS-DSP (University of Tehran and Iran Communicaton Industries (SAMA)) IC which has been designed in VLSI Circuits and Systems Laboratory.     

边界扫描技术在含DSP电路板测试与诊断的研究与应用

针对含DSP电路板的测试与诊断问题,本文提出一种利用边界扫描技术和传统的外部输入矢量测试相结合的方法,对含DSP电路板中的边界扫描器件的器件及非边界扫描器件进行了测试.测试结果表明:该测试方法对边界扫描器件及非边界扫描器件可进行有效的故障检测和故障隔离,并可将故障隔离至最小的测试单元.同时详细阐述了测试诊断方案、硬件设...     

Efficient hardware controller synthesis for synchronous dataflow graph in system level design

This paper concerns automatic hardware synthesis from data flow graph (DFG) specification in system level design. In the presented design methodology, each node of a data flow graph represents a hardware library module that contains a synthesizable VHDL code. Our proposed technique automatically synthesizes a clever control structure, cascaded counter controller, that supports asynchronous interaction with outside modules while efficiently implementing the synchronous dataflow semantics of the graph at the same time. Through comparison with previous works with some examples, the novelty of the proposed technique is demonstrated.     

基于专用芯片的微波电路模块嵌入式测试设计验证

本文提出一种基于专用芯片的微波电路模块嵌入式测试设计方法,来解决微波电路测试难以接入、故障诊断困难的技术难题,文中阐述了微波电路模块嵌入式测试设计的思路及其硬件设计与软件设计方法,并针对基于专用芯片的微波电路模块嵌入式测试设计进行了验证。     

地址数据复用型Flash存储器测试技术研究

随着半导体技术的迅猛发展,移动存储设备快速增长。Flash芯片作为移动存储设备中最常用的器件,得到了日趋广泛的应用,对Flash芯片的测试要求也越来越高。地址数据复用型Flash存储器测试技术研究及电路设计,设计改善大规模数字集成电路测试系统数字系统算法图形功能。对K9F2G08R0A进行了测试并通过对数字系统算法图形功能进行改善,算法图形发生器由多个算术逻辑单元、多路选择器以及操作寄存器组成,可以实现复杂的逻辑操作和算术运算,可以更快、更简便地对地址复用型Flash存储器进行测试,减少测试程序开发难度。     

SD卡存储模块设计

在SD存储卡设计讨论的基础上给出了实现过程,讨论开发平台.围绕提高速度设计和实现了系统架构,开发环境,基本模块设计和读写模块设计.通过这样的实现,可以使读写的速度达到20MB/s、12MB/s.通过W86L388D桥接芯片,控制器和Nand Flash芯片两块大的芯片实现SD长硬件部分.通过四大模块来设计和实现控制器,...     

The embedded design verification test of microwave circuit modules based on specific chips

In the Paper,the author introduces an embedded design verification test based on specific chips to solve the technical problems of microwave circuit test and fault diagnosis.The author explains embedded design of microwave circuit modules and approach of hardware design and software design,and finally verifies the embedded design of microwave circuit modules based on specific chips.     

Fast Enhancement of Validation Test Sets for Improving the Stuck-at Fault Coverage of RTL Circuits

A digital circuit usually comprises a controller and datapath. The time spent for determining a valid controller behavior to detect a fault usually dominates test generation time. A validation test set is used to verify controller behavior and, hence, it activates various controller behaviors. In this paper, we present a novel methodology wherein the controller behaviors exercised by test sequences in a validation test set are reused for detecting faults in the datapath. A heuristic is used to identify controller behaviors that can justify/propagate pre-computed test vectors/responses of datapath register-transfer level (RTL) modules. Such controller behaviors are said to be compatible with the corresponding precomputed test vectors/responses. The heuristic is fairly accurate, resulting in the detection of a majority of stuck-at faults in the datapath RTL modules. Also, since test generation is performed at the RTL and the controller behavior is predetermined, test generation time is reduced. For microprocessors, if the validation test set consists of instruction sequences then the proposed methodology also generates instruction-level test sequences.     

FPGA Implementation of Embedded Fuzzy Controllers for Robotic Applications

Fuzzy-logic-based inference techniques provide efficient solutions for control problems in classical and emerging applications. However, the lack of specific design tools and systematic approaches for hardware implementation of complex fuzzy controllers limits the applicability of these techniques in modern microelectronics products. This paper discusses a design strategy that eases the implementation of embedded fuzzy controllers as systems on programmable chips. The development of the controllers is carried out by means of a reconfigurable platform based on field-programmable gate arrays. This platform combines specific hardware to implement fuzzy inference modules with a general-purpose processor, thus allowing the realization of hybrid hardware/software solutions. As happens to the components of the processing system, the specific fuzzy elements are conceived as configurable intellectual property modules in order to accelerate the controller design cycle. The design methodology and tool chain presented in this paper have been applied to the realization of a control system for solving the navigation tasks of an autonomous vehicle.     

An architectural level test generator based on nonlinear equation solving

It has been shown that the hierarchy of large VLSI circuits can be exploited to speed up the test generation process. However, severe problems remain in most of the published literature which were based on a high level branch-and-bound approach. When the circuit module diagram is complex, it is very difficult to formalize the high level knowledge derived from the circuit hierarchy to make successful decisions in searching. Whenever a global path conflict or value conflict happens, it is unlikely that the backtracking scheme is able to solve this conflict through high level knowledge manipulation. In this article, a new architectural level test generation algorithm based on a nonlinear equation-solving methodology is proposed to solve conflicts and avoid making high level decisions when the tests are computed. For each pattern to be justified at a high level, an instruction sequence and the under-determined system of nonlinear equations are derived based on preprocessing information. The solution of the system of equations are calculated by a signal-driven discrete relaxation algorithm without making any high level decision. The test generation is performed by recursively assembling the instruction sequence and solving the system of equations. This new test generation approach has been implemented, and the tests of several microprocessors have been generated successfully. The results show that this approach is effective and promising.This research was supported by the Semiconductor Research Corporation under Contract SRC 91-DP-109. A preliminary version of this paper appeared in ICCAD-91.     

Statistical Tolerance Analysis for Assured Analog Test Coverage

Increasing numbers of analog components in today's systems necessitate system level test composition methods that utilize on-chip capabilities rather than solely relying on costly DFT approaches. We outline a tolerance analysis methodology for test signal propagation to be utilized in hierarchical test generation for analog circuits. A detailed justification of this proposed novel tolerance analysis methodology is undertaken by comparing our results with detailed SPICE Monte-Carlo simulation data on several combinations of analog modules. The results of our experiments confirm the high accuracy and efficiency of the proposed tolerance analysis methodology.     

星载SAR实时成像处理器的FPGA实现

本文提出了一种用FPGA实现星载合成孔径雷达实时成像处理器的方法,用来实现星载SAR的CS算法(或RMA算法).该实时成像处理器由7片Xilinx公司的商业FPGA实现,其中4片作为并行的处理单元;一片为CS因子的生成单元;一片为SDRAM控制单元;一片为系统的控制单元.该系统将流水处理和并行处理相结合,从而极大的减少了处理时间.同时根据算法各运算对数据的精度要求不同,将浮点运算和定点运算结合在一块,减少了硬件开销.该系统工作在100MHz时,33秒左右能完成16k*16k星载样本点的成像,并对加拿大Radarsat的雷达原始信号进行成像处理,成像质量能达到要求.     

VLSI流水化格型数字滤波器的内建自测试

格型数字滤波器在信号处理领域得到了广泛应用,本文针对VLSI实现的流水化格型数字滤波器,提出了一种内建自测试方案,不需要对其内部基本功能单元作任何更改,且能在较短时间内检测所有的单固定型故障.所有测试序列都采用简单的算术运算产生.通过对已有功能模块如累加器的复用,作为测试序列生成和响应压缩,该方案能实现真速测试并最大程度的减少了硬件占用和系统性能占用.