DTMB系统中BCH译码算法及其FPGA实现

首先证明了DTMB系统中采用的BCH码是纠错能力为1的循环汉明码,并基于此提出了适用于该BCH码的译码算法,及其串行和并行两种FPGA实现电路.考虑到该BCH缩短码的特性,通过修改差错检测电路,使其译码时延缩短34％.实验结果表明,译码器译码正确无误,FPGA资源占用极少.串行译码器总时延为762个时钟周期,最大工作时钟频率可达357 MHz.并行译码器总时延仅为77个时钟周期,最大工作时钟频率可达276 MHz.     

循环汉明码编译码器的设计与FPGA实现

分析了循环码的特性,提出一种循环汉明码编译码器的设计方案。编译码器中编码采用除法电路,译码采用梅吉特译码器,易于工程应用。对编译码器在FPGA上进行了实现,通过参数化设置,具有较高的码率,适用于(255,247)及其任意缩短码的循环汉明码,并给出了译码器的仿真和测试结果。结果表明:编译码器运行速率高、译码时延小,在Virtex-5芯片上,最高工作时钟频率大于270 MHz。在码组错误个数确定的系统应用中,可以有效降低误码率,一般可将误码率降低一个量级。实践表明,该设计具有很强的工程实用价值。     

高速光通信中的级联码设计与VLSI实现

本文设计了应用于光通信系统的RS(255,239)+BCH(2184,2040)级联码编解码电路。级联码系统中,RS码与BCH码速度的不匹配是影响性能的最大瓶颈,本文采用并行度为8的并行BCH编解码器来实现与RS码速度的匹配。推导了BCH编码器并行化方法,并利用子项共享的方法来减少子项的扇出,使每个子项的最大扇出数不超过10。利用并行伴随式计算和并行钱氏搜索来提高BCH译码器的吞吐量,同时充分利用截短码的特性使钱氏搜索时间减少了46%。级联码的编解码器已用TSMC 0.18-μmCMOS标准单元库方法实现,后仿真结果表明,在312.5MHz的时钟下,级联码能够正常工作,能实现2.5Gb/s的数据吞吐量。建立了基于Xilinx FPGA的测试验证平台,测试结果表明电路功能正确、工作正常。     

快速收敛的EG-LDPC译码算法设计实现

欧式几何构造的LDPC码属于不可分层的LDPC码,无法采用TDMP算法译码结构,针对该问题设计实现了一种新型分层译码器。在Xilinx V5 FPGA上实现了码长为1023、码率为0.781 EG-LDPC 码的译码器设计。仿真验证表明：理论上该方法与优化的规范化最小和译码算法相比,迭代次数减少一倍,存储资源消耗得到降低,而误码性能几乎相同。FPGA实现上,译码输出与MATLAB定点仿真给出的结果相同,误码性能由于量化和限幅处理与理论值相比约有0.3dB的损失。在时钟频率为50MHz串行处理各分层时,吞吐量为49.7Mbps。     

DTMB中LDPC码编译码器的FPGA实现

针对数字地面多媒体广播标准中的低密度奇偶校验(LDPC)码,设计实现了基于现场可编程逻辑门阵列(FPGA)的LDPC码编译码器。设计所采用的编译码器方案均采用部分并行结构,在吞吐量与硬件复杂度之间达到了较好的折中。进一步,实现了用于LDPC码性能测试的误码测试硬件系统。基于FPGA的硬件实现结果表明,针对码率为0.4的LDPC码,设计的编译码器可工作在160MHz的时钟频率下,以译码前的数据量计算,吞吐量达到214Mbps。当误比特率为10-6时,实现的6比特量化译码器与浮点译码器的性能差距仅为0.05d B。     

基于FPGA的不可分层LDPC码译码器

针对不可分层LDPC码无法采用分层译码算法的问题,设计了一种新型的LDPC码分层译码器。与传统分层译码器的结构不同,新结构在各层间进行并行更新,各层内进行串行更新。通过保证在不同分层的同一变量节点不同时进行更新,达到分层译码算法分层递进更新的目标。选用Altera公司的CycloneⅢ系列EP3C120器件,实现码率3/4,码长8 192的(3,12)规则不可分层QC-LDPC码译码器的布局布线,在最大迭代次数为5次时,最高时钟频率可以达到45.44 MHz,吞吐量可以达到47.6 Mbps。     

可变码率BCH码编译码的FPGA实现

为了克服LDPC的误码平台,可采用BCH码与LDPC的级联。在参考了多种编译码结构的基础上,针对二进制BCH码,介绍了适合码率可变的编译码方法,包括短时延的编码,译码中的伴随式计算、错误位置多项式的计算、错误位置的求解、逆元素的求解和相关控制存储等模块所采用的算法及FPGA实现的硬件结构。通过测试,该算法结构占用FPGA资源适中,整体硬件实现可靠,在工作时钟为150MHz时,数据吞吐速率达到100MHz以上。     

BCH码译码器的FPGA实现

在通信领域,差错控制技术能有效地改善通信系统的传输性能。作者在本文中探讨了BCH码的译码算法,并用Altera FPGA 实现了BCH(31,21)码的两种硬件译码。一种是串行译码;另一种是并行译码。取得了令人满意的结果。     

一种合并状态度量计算的高效并行Turbo码译码器结构设计及FPGA实现

为满足无线通信中高吞吐、低功耗的要求,并行译码器的结构设计得到了广泛的关注。基于并行Turbo码译码算法,研究了前后向度量计算中的对称性,提出了一种基于前后向合并计算的高效并行Turbo码译码器结构设计方案,并进行现场可编程门阵列(field-programmable gate array,FPGA)实现。结果表明,与已有的并行Turbo码译码器结构相比,本文提出的设计结构使状态度量计算模块的逻辑资源降低50%左右,动态功耗在125 MHz频率下降低5.26%,同时译码性能与并行算法的译码性能接近。     

采用C语言FPGA技术实现LDPC码译码算法

针对LDPC码(Low Density Parity Check Codes)译码算法的特点和最新一代Impulse C语言的并行编程技术,提出一种对LDPC码译码器进行FPGA(Field Programmable Gate Array)设计与实现的便捷新方案,以获得译码速率和硬件资源消耗的平衡.在XC2V2000芯片上实现了一种码率1/2,码长2500的(3,6)LDPC码译码器.实验表明当最大迭代次数为10次,主频50MHz时,译码速率可达10Mbps.     

基于FPGA的高速Viterbi译码器设计与实现

Viterbi算法是卷积码最常用的译码算法,在卷积码约束长度较大,译码时延要求较高的场合,如何实现低硬件复杂度的Viterbi译码器成为新的课题。本文提出新颖的Viterbi路径权重算法、双蝶形译码单元结构、高效的状态度量存储器等技术,使Viterbi算法充分和FPGA灵活原片内存储和逻辑单元配置方法相结合,发挥出最佳效率。用本算法在32MHz时钟下实现的256状态的Viterbi译码器译码速率可达400Kbps以上,且仅占用很小的硬件资源,可以方便地和Furbo译码单元等集成在单片FPGA,形成单片信道译码单元。     

基于FPGA有限域构造的QC-LDPC分层译码器设计

针对QC-LDPC码的Tanner图中存在的短环,尤其是4环,对迭代译码性能产生不利影响的问题,寻找到一种有限域乘群构造法,该方法构造的QC-LDPC码的Tanner图中不存在任何4环。基于此方法构造的码长为3 060,码率为的(3,12)规则QC-LDPC码,选用Altera公司StratixII系列的EP2S60F484C4器件,对其实现了分层译码器硬件结构的设计。实现结果表明,在最大迭代次数为5时,时钟频率最高可达35.38 MHz,吞吐量达到92.27 Mbit·s-1。     

Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder

We present an efficient VLSI architecture for 3GPP LTE/LTE-Advance Turbo decoder by utilizing the algebraic-geometric properties of the quadratic permutation polynomial (QPP) interleaver. The high-throughput 3GPP LTE/LTE-Advance Turbo codes require a highly-parallel decoder architecture. Turbo interleaver is known to be the main obstacle to the decoder parallelism due to the collisions it introduces in accesses to memory. The QPP interleaver solves the memory contention issues when several MAP decoders are used in parallel to improve Turbo decoding throughput. In this paper, we propose a low-complexity QPP interleaving address generator and a multi-bank memory architecture to enable parallel Turbo decoding. Design trade-offs in terms of area and throughput efficiency are explored to find the optimal architecture. The proposed parallel Turbo decoder has been synthesized, placed and routed in a 65-nm CMOS technology with a core area of 8.3 mm² and a maximum clock frequency of 400 MHz. This parallel decoder, comprising 64 MAP decoder cores, can achieve a maximum decoding throughput of 1.28 Gbps at 6 iterations     

光存储RS译码器设计与译码速度分析

比较了reed-solomon（RS）译码的Berlekamp-Massey（BM）算法和Euclidean算法的运行速度,并选择BM算法设计了满足36Mbps数据传输率（D豫）的RS译码器。针对现有几种光盘的DTR,进一步分析了光存储中RS译码速度的要求,并对译码中的有限域乘法器做了仿真。该乘法器在工作频率为50MHz的FPGA芯片中工作正常,可以满足光盘的DTR要求。     

High-throughput layered decoder implementation for quasi-cyclic LDPC codes

This paper presents a high-throughput decoder design for the Quasi-Cyclic (QC) Low-Density Parity-Check (LDPC) codes. Two new techniques are proposed, including parallel layered decoding architecture (PLDA) and critical path splitting. PLDA enables parallel processing for all layers by establishing dedicated message passing paths among them. The decoder avoids crossbar-based large interconnect network. Critical path splitting technique is based on articulate adjustment of the starting point of each layer to maximize the time intervals between adjacent layers, such that the critical path delay can be split into pipeline stages. Furthermore, min-sum and loosely coupled algorithms are employed for area efficiency. As a case study, a rate-1/2 2304-bit irregular LDPC decoder is implemented using ASIC design in 90nm CMOS process. The decoder can achieve the maximum decoding throughput of 2.2Gbps at 10 iterations. The operating frequency is 950MHz after synthesis and the chip area is 2.9mm².     

A Flexible LDPC/Turbo Decoder Architecture

Low-density parity-check (LDPC) codes and convolutional Turbo codes are two of the most powerful error correcting codes that are widely used in modern communication systems. In a multi-mode baseband receiver, both LDPC and Turbo decoders may be required. However, the different decoding approaches for LDPC and Turbo codes usually lead to different hardware architectures. In this paper we propose a unified message passing algorithm for LDPC and Turbo codes and introduce a flexible soft-input soft-output (SISO) module to handle LDPC/Turbo decoding. We employ the trellis-based maximum a posteriori (MAP) algorithm as a bridge between LDPC and Turbo codes decoding. We view the LDPC code as a concatenation of n super-codes where each super-code has a simpler trellis structure so that the MAP algorithm can be easily applied to it. We propose a flexible functional unit (FFU) for MAP processing of LDPC and Turbo codes with a low hardware overhead (about 15% area and timing overhead). Based on the FFU, we propose an area-efficient flexible SISO decoder architecture to support LDPC/Turbo codes decoding. Multiple such SISO modules can be embedded into a parallel decoder for higher decoding throughput. As a case study, a flexible LDPC/Turbo decoder has been synthesized on a TSMC 90 nm CMOS technology with a core area of 3.2 mm². The decoder can support IEEE 802.16e LDPC codes, IEEE 802.11n LDPC codes, and 3GPP LTE Turbo codes. Running at 500 MHz clock frequency, the decoder can sustain up to 600 Mbps LDPC decoding or 450 Mbps Turbo decoding.     

Fast-Converging and Low-Power LDPC Decoding: Algorithm,Architecture, and VLSI Implementation

Low-latency and energy-efficient multi-Gbps LDPC decoding requires fast-converging iterative schedules. Hardware decoder architectures based on such schedules can achieve high throughput at low clock speeds, resulting in reduced power consumption and relaxed timing closure requirements for physical VLSI design. In this work, a fast column message-passing (FCMP) schedule for decoding LDPC codes is presented and investigated. FCMP converges in half the number of iterations compared to existing serial decoding schedules, has a significantly lower computational complexity than residual-belief-propagation (RBP)-based schedules, and consumes less power compared to state-of-the-art schedules. An FCMP decoder architecture supporting IEEE 802.11ad (WiGig) LDPC codes is presented. The decoder is fully pipelined to decode two frames with no idle cycles. The architecture is synthesized using the TSMC 40 nm and 65 nm CMOS technology nodes, and operates at a clock-frequency of 200 MHz. The decoder achieves a throughput of 8.4 Gbps, and it consumes 72 mW of power when synthesized using the 40 nm technology node. This results in an energy efficiency of 8.6 pJ/bit, which is the best-reported energy-efficiency in the literature for a WiGig LDPC decoder.