Design of high-speed two-stage cascode-compensated operational amplifiers based on settling time and open-loop parameters

Settling behavior of operational amplifiers is of great importance in many applications. In this paper, an efficient methodology for the design of high-speed two-stage operational amplifiers based on settling time is proposed. Concerning the application of the operational amplifier, it specifies proper open-loop circuit parameters to obtain the desired settling time and closed-loop stability. As the effect of transfer function zeros has been taken into account, the proposed methodology becomes more accurate in achieving the desired specifications. Simulation results are presented to show the effectiveness of the methodology.     

Design Procedure for Settling Time Minimization in Three-Stage Nested-Miller Amplifiers

Low-power, low-voltage, and high-performance requirements are badly needed for operational amplifiers (op-amps) in modern applications. In this brief, a design method for minimizing the settling time in three-stage nested-Miller schemes is presented. As an application example, a CMOS 0.35-mum voltage follower with 115-dB dc gain and fastest step response to 1% accuracy level, is designed. Circuital simulations demonstrate that the proposed procedure allows the amplifier settling-time/power-consumption ratio to be significantly improved with respect to conventionally designed op-amps.     

A Network Modeling and Design Method for a 2- 18-Ghz Feedback Amplifier

An accurate network theory and modeling method, including feedback loop circuit parasitic and device limitations, is presented for the design of broad-band microwave feedback amplifiers. Discussed are circuit realization and measured performance in relation to VSWR, gain flatness, and stability of a 2-18-GHz three-stage amplifier.     

A new fast settling low power CMOS gain stage architecture

This paper presents a new gain stage for high accuracy and fast settling applications. In the proposed structure a novel combination of closed loop and open loop amplifiers is employed to achieve high accuracy and enhanced settling behavior while adding only negligible power to the main circuit power constraint. To evaluate the functionality of the proposed idea, a zero cross based circuit and a switch capacitor amplifier are designed to implement the open loop and the closed loop stages, respectively. Though, other topologies for implementation of open loop and closed loop amplifiers are applicable in the presented gain stage. The proposed structure is implemented in 0.18 μm CMOS technology. HSPICE simulation results, using level 49 models, demonstrate that the new configuration improves the power efficiency and the settling behavior as well as the system accuracy. The proposed scheme shows very fast settling times of 0.8, 1.01, 1.41 ns for the gain accuracies of 6, 8 and 10 bits, respectively, while loaded with 1 pF capacitance and the output swing is 1.6 V. In comparison with a conventional switched capacitor closed loop amplifier, the proposed architecture improves the settling performance by a factor of 3 for 6 bit resolution, while it adds only 0.63 mW power to the total power consumption that is 8.68 mW.     

Positive feedback frequency compensation for low-voltage low-power three-stage amplifier

The use of a new frequency compensation scheme for a three-stage operational amplifier is presented. The use of a positive feedback compensation (PFC) is employed to improve frequency response when compared to nested Miller compensation. A set of design equations is derived to give insight into the sizing of the amplifier. In addition, some characteristics relevant to the low-voltage low-power circuits using operational amplifiers have been modeled. Finally, an optimization algorithm was used with the purpose of extracting the most efficient solution. The PFC is especially suitable for driving large capacitance loads. It improves frequency response, slew rate (SR), and settling time. Small compensation capacitors make it appropriate for integration in commercial CMOS processes. With an active area of 0.03 mm/sup 2/ and working at 1.5 V, the circuit dissipates 275 /spl mu/W, has more than a 100-dB gain, a gain bandwidth of 2.7 MHz, and 1.0 V/spl mu/s average SR while driving a 130-pF load. Both measured frequency and transient step response show that the amplifier is stable.     

超宽带低噪声放大器的计算机辅助设计

叙述了超宽带低噪声放大器的计算机辅助设计方法，提出了利用普通微带混合集成电路．工艺设计超宽带低噪声放大器的方法和关键技术，并且用带封装的ＢＪＴ和ＦＥＴ实现了两个超宽带低噪声放大器。实验结果和设计结果吻合较好。一个利用２ＳＣ３３５８，放大器为三级，频带为３０ｋＨＺ～１６００ＭＨＺ，增益Ｇ＝２０±１ｄＢ，噪声系数ＮＦ≤３．５ｄＢ；另一个利用ＡＴＦ１０２３５（６），放大器为二级，频带为５００ｋＨＺ～６０００ＭＨＺ，增益Ｇ＝２０±２ｄＢ，噪声系数ＮＦ≤２ｄＢ。     

Advances in active-feedback frequency compensation with power optimization and transient improvement

This paper presents a low-power stability strategy to significantly reduce the power consumption of a three-stage amplifier using active-feedback frequency compensation (AFFC). The bandwidth of the amplifier can also be enhanced. Simulation results verify that the power dissipation of the AFFC amplifier is reduced by 43% and the bandwidth is improved by 32.5% by using the proposed stability strategy. In addition, a dynamic feedforward stage (DFS), which can be embedded into the AFFC amplifier to improve the transient responses without consuming extra power, is proposed. Implemented in a 0.6-/spl mu/m CMOS process, experimental results show that both AFFC amplifiers with and without DFS achieve almost the same small-signal performances while the amplifier with DFS improves both the negative slew rate and negative 1% settling time by two times.     

Miller Compensation: Optimal Design for Operational Amplifiers with a Required Settling Time

Optimizing the settling response of an operational amplifier can be a serious design issue in today’s low-power CMOS technologies. Several design challenges emerge when improving the linear and nonlinear responses of an amplifier. In this paper, we developed a settling model for use in design and optimization of two-stage Miller-compensated amplifiers. Using this model, the closed-form relations between settling time/settling error, gain-bandwidth product, noise, power and stability have been obtained. These relations are employed to form a settling-based design routine for Miller-compensated amplifiers. Simulation results in 0.18- \(\upmu \) m CMOS validate the effectiveness of the proposed routine. In a design prototype, it predicts the settling time with an error less than 3 %. In another design example, the relationship between settling time and gain-bandwidth has been evaluated with an accuracy higher than 95 %. The proposed design routine is used to implement a 40 MS/s sample-and-hold amplifier. It achieves a settling time and signal-to-noise-plus-distortion ratio equal to 12.5 ns and 82 dB, respectively.     

Monolithic GaAs transimpedance amplifiers for fiber-optic receivers

The authors describe the design of transimpedance amplifiers using GaAs MESFET technology. A GaAs transimpedance preamplifier for fiber-optic receivers has been fabricated with two gain stages and an inducer-FET load structure that reduces noise. The two-stage amplifier design provides increased open-loop gain as compared with a single-stage design, and greater closed-loop stability than a three-stage amplifier. An automatic-gain-control (AGC) circuit that varied the value of the feedback resistor was incorporated into the design     

Design procedure for optimizing CMOS low noise operational amplifiers

This paper presents and experimentally verifies an optimized design procedure for a CMOS low noise operational amplifier.The design procedure focuses on the noise performance,which is the key requirement for low noise operational amplifiers.Based on the noise level and other specifications such as bandwidth,signal swing,slew rate,and power consumption,the device sizes and the biasing conditions are derived.In order to verify the proposed design procedure,a three-stage operational amplifier has been designed.The device parameters obtained from the proposed design procedure closely agree with the simulated results obtained by using HSPICE.     

低噪声CMOS运算放大器的优化设计方法

This paper presents and experimentally verifies an optimized design procedure for a CMOS low noise operational amplifier. The design procedure focuses on the noise performance, which is the key requirement for low noise operational amplifiers. Based on the noise level and other specifications such as bandwidth, signal swing, slew rate, and power consumption, the device sizes and the biasing conditions are derived. In order to verify the proposed design procedure, a three-stage operational amplifier has been designed. The device parameters obtained from the proposed design procedure closely agree with the simulated results obtained by using HSPICE.     

Two digitally programmable gain amplifiers based on current conveyors

Two digitally programmable gain amplifiers based on current conveyors (CCIIs) are presented. The first digitally programmable gain amplifier consists of a CCII, an operational transconductance amplifier (OTA), and current mirrors. The second one is composed of current conveyor analogue switches (CCASs). Both proposed digitally programmable gain amplifiers do not need switches but they maintain the linear gain at any digital signal levels similar to the digitally programmable gain amplifier using switches; hence the proposed amplifiers are easier to realize, use narrower chip area, and consume lower power. The first proposed amplifier is verified by constructing the circuit using the CCII in an AD844 IC, the OTA in a CA3080 IC, and some bipolar current mirrors. The second proposed amplifier is verified by simulating the circuit using the parameters extracted from the layout (including parasitic capacitance) in the 0.25 μm MOS technology, the level 49 MOS model obtained through MOSIS is used. The results show that the operations of two proposed amplifiers are in accordance with the theories.     

适用于电子倍增器件的电荷灵敏放大器的设计

介绍了一种自主研制的新型电荷灵敏型三级放大器,其电路设计主要采用ADA4817高速低噪声集成运算放大芯片,该三级放大器噪声低、稳定性好、电路结构简单、性价比高、检修更换方便,可以不失真地放大上升时间在ns级的信号,放大器输出信号质量优异,可配合后续的多道分析器MCA8000D读取微通道板（microchannel plate,MCP）组件或单通道电子倍增器（single-channel electron multiplier,CEM）的单光电子谱,测试结果表明:自主设计的ADA4817型放大器在一定的方波标定脉冲信号下,其基线的宽度小于2 mV,上升沿时间约为800 ns,幅值约为40 mV,性能接近或略优于A250型放大器,可以更好地配合后续的多道分析器MCA8000D进行输出波形的分析和处理,完全满足MCP或CEM探测器的脉冲性能测试需求。     

Efficient switched-capacitor common-mode feedback circuit for high-speed low-power amplifiers

A new switched-capacitor (SC) common-mode feedback (CMFB) circuit for fully-differential operational amplifiers (op-amps) is presented. By reducing the amplifier capacitive load with respect to conventional SC-CMFB schemes, the proposed solution guarantees a significant improvement of the op-amp speed performance. A typical SC integrator employing the new CMFB has also been designed in 0.35 μm CMOS technology. Simulation results show that, for a given power consumption, the op-amp settling time can be about halved by using the proposed CMFB instead of the conventional one.     

A dual-path bandwidth extension amplifier topology with dual-loop parallel compensation

A dual-path amplifier topology with dual-loop parallel compensation technique is proposed for low-power three-stage amplifiers. By using two parallel high-speed paths for high-frequency signal propagation, there is no passive capacitive feedback network loaded at the amplifier output. Both the bandwidth and slew rate are thus significantly improved. Implemented in a 0.6-/spl mu/m CMOS process, the proposed three-stage amplifier has over 100-dB gain, 7-MHz gain-bandwidth product, and 3.3-V//spl mu/s average slew rate while only dissipating 330 /spl mu/W at 1.5 V, when driving a 25-k/spl Omega///120-pF load. The proposed amplifier achieves at least two times improvement in bandwidth-to-power and slew-rate-to-power efficiencies than all other reported multistage amplifiers using different compensation topologies.     

Modified Model for Settling Behavior of Operational Amplifiers in Nanoscale CMOS

An accurate time-domain model for the settling behavior of folded-cascode operational amplifiers is presented. Using a velocity–saturation model for MOS transistors makes the proposed model suitable for nanoscale CMOS technologies. Both linear and nonlinear settling regimes and their combination are considered. Transistor-level HSPICE simulation results of a fully differential single-stage folded-cascode amplifier using BSIM4v3 models of a standard 90-nm CMOS process are presented to verify the accuracy of the proposed models.      

A low-powerlow-voltage slew-rate enhancement circuit for two-stage operational amplifiers

正A novel circuit is presented in order to enhance the slew rate of two-stage operational amplifiers.The enhancer utilizes the class-AB input stage to improve current efficiency,while it works on an open loop with regard to the enhanced amplifier so that it has no effect on the stability of the amplifier.During the slewing period,the enhancer detects input differential voltage of the amplifier,and produces external enhancement currents for the amplifier,driving load capacitors to charge/discharge faster.Simulation results show that,fora large input step,the enhancerreduces settling time by nearly 50%.When the circuit is employed in a sample-and-hold circuit,it greatly improves the spur-free dynamic range by 44.6 dB and the total harmonic distortion by 43.9 dB.The proposed circuit is very suitable to operate under a low voltage(1.2 V or below) with a standby current of 200μA.     

4GHz 80K FET放大器

本文从低噪声FET放大器的实际设计出发,分析了输入匹配电路对噪声性能的影响.从放大器的实际结构讨论了影响放大器噪声性能的因素.使用南京固体器件研究所研制的WC61GaAs MESFET,在3.7～4.2GHz下,得到的结果为:两级放大器增益28dB,三级放大器增益40dB,带内噪声温度小于80K,最小噪声温度为77K.     

Active-feedback frequency-compensation technique for low-power multistage amplifiers

An active-feedback frequency-compensation (AFFC) technique for low-power operational amplifiers is presented in this paper. With an active-feedback mechanism, a high-speed block separates the low-frequency high-gain path and high-frequency signal path such that high gain and wide bandwidth can be achieved simultaneously in the AFFC amplifier. The gain stage in the active-feedback network also reduces the size of the compensation capacitors such that the overall chip area of the amplifier becomes smaller and the slew rate is improved. Furthermore, the presence of a left-half-plane zero in the proposed AFFC topology improves the stability and settling behavior of the amplifier. Three-stage amplifiers based on AFFC and nested-Miller compensation (NMC) techniques have been implemented by a commercial 0.8-/spl mu/m CMOS process. When driving a 120-pF capacitive load, the AFFC amplifier achieves over 100-dB dc gain, 4.5-MHz gain-bandwidth product (GBW) , 65/spl deg/ phase margin, and 1.5-V//spl mu/s average slew rate, while only dissipating 400-/spl mu/W power at a 2-V supply. Compared to a three-stage NMC amplifier, the proposed AFFC amplifier provides improvement in both the GBW and slew rate by 11 times and reduces the chip area by 2.3 times without significant increase in the power consumption.