A new active RF phase shifter using variable gain, drain Voltage controlled PHEMTs:A 2.4-GHz ISM implementation

Phase shifters operating at RF bands are an essential component of phased and adaptive arrays circuits. In this letter, an active phase shifter is proposed, using vector summing of an in-phase and a quad-phase replica of the incoming signal. The proposed scheme was designed and implemented using a Wilkinson power combiner/divider, a branch line hybrid coupler and single-stage variable gain amplifiers (VGAs), achieving continuous phase shift within the range of [0/spl deg/, 90/spl deg/]. The manufactured prototype is suitable for WLAN operations in the 2.4-GHz ISM band. Details of the phase shifter design and experimental results are presented.     

A 4-bit CMOS Phase Shifter Using Distributed Active Switches

This paper presents a novel 4-bit phase shifter using distributed active switches in 0.18-mum RF CMOS technology. The relative phase shift, which varies from 0deg to 360deg in steps of 22.5deg, is achieved with a 3-bit distributed phase shifter and a 180deg high-pass/low-pass phase shifter. The distributed phase shifter is implemented using distributed active switches that consist of a periodic placement of series inductors and cascode transistors, thereby obtaining linear phase shift versus frequency with a digital control. The design guideline of the distributed phase shifter is presented. The 4-bit phase shifter achieves 3.5 plusmn 0.5 dB of gain, with an rms phase error of 2.6deg at a center frequency of 12.1 GHz. The input and output return losses are less than -15 dB at all conditions. The chip size is 1880 mum times 915 mum including the probing pads.     

一种5~20 GHz超宽带移相器

基于SMIC 40 nm CMOS工艺设计了一款工作频率覆盖5 ~20 GHz的超宽带6位移相器。该移相器采用矢量合成结构,核心电路包括输入巴伦、正交信号发生器、矢量合成器和数模转换电路。正交信号发生器采用三级多相滤波结构,拓展了带宽。采用低误差和电流阵列控制结构的矢量合成器,实现了高的移相精度。后仿真结果表明,该移相器输入和输出回波损耗分别小于8.85 dB和10.12 dB,RMS相位误差小于1.52°,RMS增益误差小于0.17 dB。在2.5 V电源电压下功耗为43.50 mW。芯片面积为1.06 mm×0.80 mm。     

K-band HBT and HEMT monolithic active phase shifters using vector sum method

Two monolithic 3-bit active phase shifters using the vector sum method to K-band frequencies are reported in this paper. They are separately implemented using commercial 6-in GaAs HBT and high electron-mobility transistor (HEMT) monolithic-microwave integrated-circuit (MMIC) foundry processes. The MMIC HBT active phase shifter demonstrates an average gain of 8.87 dB and a maximum phase error of 11/spl deg/ at 18 GHz, while the HEMT phase shifter has 3.85-dB average measured gain with 11/spl deg/ maximum phase error at 20 GHz. The 20-GHz operation frequency of this HEMT MMIC is the highest among all the reported active phase shifters. The analysis for gain deviation and phase error of the active phase shifter using the vector sum method due to the individual variable gain amplifiers is also presented. The theoretical analysis can predict the measured minimum root-mean-square phase error 4.7/spl deg/ within 1/spl deg/ accuracy.     

Distributed 2- and 3-bit W-band MEMS phase shifters on glass substrates

This paper presents state-of-the-art RF microelectromechanical (MEMS) phase shifters at 75-110 GHz based on the distributed microelectromechanical transmission-line (DMTL) concept. A 3-bit DMTL phase shifter, fabricated on a glass substrate using MEMS switches and coplanar-waveguide lines, results in an average loss of 2.7 dB at 78 GHz (0.9 dB/bit). The measured figure-of-merit performance is 93/spl deg//dB-100/spl deg//dB (equivalent to 0.9 dB/bit) of loss at 75-110 GHz. The associated phase error is /spl plusmn/3/spl deg/ (rms phase error is 1.56/spl deg/) and the reflection loss is below -10 dB over all eight states. A 2-bit phase shifter is also demonstrated with comparable performance to the 3-bit design. It is seen that the phase shifter can be accurately modeled using a combination of full-wave electromagnetic and microwave circuit analysis, thereby making the design quite easy up to 110 GHz. These results represent the best phase-shifter performance to date using any technology at W-band frequencies. Careful analysis indicates that the 75-110-GHz figure-of-merit performance becomes 150/spl deg//dB-200/spl deg//dB, and the 3-bit average insertion loss improves to 1.8-2.1 dB if the phase shifter is fabricated on quartz substrates.     

A 2-bit RF MEMS phase shifter in a thick-film BGA ceramic package

The development of a thick-film hermetic BGA package for a radio-frequency (RF) microelectromechanical systems (MEMS) 2-bit phase shifter is presented. The measured packaged MEMS phase shifter average in-band insertion loss was 1.14 dB with an average return loss of 15.9 dB. The package transition insertion loss was less than 0.1 dB per transition with excellent agreement between simulated and measured results. It was also demonstrated that the RF MEMS phase shift performance could be improved to obtain a phase error of less than 3.3 degrees. The first reported measurements of the average rise and fall times associated with a MEMS circuit (in this case a 2-bit phase shifter) were 26 and 70 /spl mu/s, respectively. The advent of packaged RF MEMS phase shifters will reduce the cost (both design and building) of future phase arrays.     

A 2-bit miniature X-band MEMS phase shifter

The design and performance of a compact low-loss X-band true-time-delay (TTD) MEMS phase shifter fabricated on 8-mil GaAs substrate is described. A semi-lumped approach using microstrip transmission lines and metal-insulator-metal (MIM) capacitors is employed for the delay lines in order to both reduce circuit size as well as avoid the high insertion loss found in typical miniaturized designs. The 2-bit phase shifter achieved an average insertion loss of -0.70 dB at 9.45 GHz, and an associated phase accuracy of /spl plusmn/1.3/spl deg/. It occupies an area of only 5 mm/sup 2/, which is 44% the area of the smallest known X-band MEMS phase shifter . The phase shifter operates over 6-14 GHz with a return loss of better than -14 dB.     

X波段GaN五位数字移相器MMIC的设计

采用0.5μm GaN HEMT工艺设计了X波段五位数字移相器的单片微波集成电路(MMIC),描述了移相器的设计过程,并进行了版图电磁仿真。该移相器采用高低通滤波器型网络和加载线型结构。利用电路匹配技术设计移相器电路的开关结构,将GaN器件的插入损耗从14 dB降至1 dB。版图仿真结果表明,在9.2 GHz~10.2 GHz频带范围内,均方根移相误差小于3.5°,插入损耗典型值为17.4 dB,回波损耗小于-12 dB,版图尺寸为5.0 mm×4.7 mm。     

Quantization Error Reduction for the Phased Array with 2-bit Phase Shifter

It has been widely believed that phased array antenna should use at least 3-bit (as phase controlling bit) phase shifter to provide the satisfactory scanning capability and the unnoticeable parasitic sidelobes. In this paper, we proposed a novel phase perturbation method, namely, virtual feed approach, derived from the general concept of the phase randomization, to improve the performance for the low-cost electronic scanning antennas with 2-bit phase shifters. By using this method, problems of scanning error at small scanning angle as well as the relatively high parasitic sidelobes at large scanning angle are solved simultaneously at acceptable performance degradation.     

有限量化精度移相器对毫米波平面相阵波束控制性能的影响

在毫米波频段由于路径损耗较大,通常采用波束成形来提高链路增益以建立稳定的连接。通常在低频段采用的数字波束成形,由于每根天线配置一条射频链路,功耗和成本较高。采用相阵架构实现射频波束成形是一种折衷的选择。本文研究了毫米波信道下移相器有限的量化精度在平面相阵单流波束控制（beam steering）中带来的性能损失。首先推导了阵列增益损失与移相器误差方差之间的理论关系,然后通过蒙特卡洛仿真验证该理论结果。从仿真结果可以看出平面相阵的增益损失可以通过增加移相器精度来减小。在通常应用中,4-bit移相器在实现平面相阵波束控制时提供了足够的增益。      

A frequency-controlled active phased array

A frequency-controlled active phased array is introduced for cost-effective base-station applications. The array realizes simple LO-controlled beam steering with a fixed RF frequency, but without phase shifter components. Primary beam squint and pattern distortions, often seen in typical frequency-controlled phased arrays, are substantially reduced by the use of our heterodyne-mixing scheme and new feed network structures. The MMIC amplifiers provide more than 20 dB gain for a desired RF signal at 20 GHz, and effectively suppress the unwanted sideband and spurious LO by more than 40 dB. The K-band transmitter array demonstrates up to 40 degree beam-steering within 0.5 degree scan error and less than 1.3 dB gain error during scanning.     

A Ka-band low power consumption MMIC core chip for T/R modules

This paper presents a Ka-band low power consumption MMIC core chip using commercial 0.15 μm D-mode GaAs pHEMT technology for T/R modules. The core chip consists of two linear gain amplifiers, a SPDT switch, a 5-bit attenuator and a 5-bit phase shifter with a size of 4.8 mm × 2.5 mm. In the receiving mode, the 32–38 GHz core chip results in a gain of 9.0 dB and an output P_1dB of –3 dBm. In the transmitting mode, the gain and output P_1dB are 11.5 dB and +0 dBm, respectively. The measured rms attenuation error and phase error are 0.7 dB and 3.8°. The power consumption is 150 mW in both work modes. The measured results show that the operating bandwidth, power consumption, gain, rms attenuation error and phase error have been significantly improved compared with the previous reports.     

A 77-GHz Phased-Array Transceiver With On-Chip Antennas in Silicon: Receiver and Antennas

In this paper, we present the receiver and the on-chip antenna sections of a fully integrated 77-GHz four-element phased-array transceiver with on-chip antennas in silicon. The receiver section of the chip includes the complete down-conversion path comprising low-noise amplifier (LNA), frequency synthesizer, phase rotators, combining amplifiers, and on-chip dipole antennas. The signal combining is performed using a novel distributed active combining amplifier at an IF of 26 GHz. In the LO path, the output of the 52-GHz VCO is routed to different elements and can be phase shifted locally by the phase rotators. A silicon lens on the backside is used to reduce the loss due to the surface-wave power of the silicon substrate. Our measurements show a single-element LNA gain of 23 dB and a noise figure of 6.0dB. Each of the four receive paths has a gain of 37 dB and a noise figure of 8.0 dB. Each on-chip antenna has a gain of +2 dBi     

Photonic RF phase shifter for harmonic downconversion in phasedarray antenna beam-forming applications

A photonic integrated-optic RF phase shifter for harmonic downconversion in phased array antenna beam-forming applications is presented. The subsystem consists of two integrated optic Mach-Zehnder interferometers fed with a combined signal from the receiving antenna and the local oscillator. This device achieves both phase shifting and harmonic downconversion of incoming RF signals     

一种6~18 GHz宽带高精度有源移相器

设计了一种6 bit 6~18 GHz工作频段的宽带高精度有源移相器。片上集成了输入无源巴伦、逻辑编码器、RC多相滤波器、矢量合成单元、数控单元等。该移相器的设计采用55 nm CMOS工艺实现,芯片尺寸为1.29 mm×0.9 mm,移相器核心尺寸为1.02 mm×0.58 mm。后仿结果表明,在6~18 GHz频率范围内,增益误差RMS值小于1 dB,相位误差RMS值小于0.75°,输入回波损耗、输出回波损耗分别小于-8.5 dB、-8.9 dB,芯片总功耗为20.7 mW。该6 bit移相器的相对带宽为100%,覆盖C、X和Ku波段,适用于雷达探测等领域。     

开关线型四位数字MEMS移相器

介绍了一种基于射频微机械串联开关设计的开关线型四位数字微机电系统(M icro-e lectrom echan ica lSystem s以下简称M EM S)移相器。该移相器集成了16个RF M EM S开关,使用了13组四分之一波长传输线和M IM接地耦合电容,有效地使开关的驱动信号和微波信号隔离,串联容性开关设计有效地降低了开关的启动电压。使用低温表面微机械工艺在360μm厚的高阻硅衬底上制作移相器,芯片尺寸4.8 mm×7.8 mm。移相器样品在片测试结果表明,频点10.1 GH z,22.5°相移位的相移误差为±0.4,°插损2.8 dB;45°位的相移误差为±1.1,°插损2.0 dB;在X波段,对16个相移态的测试结果表明,移相器的插入损耗小于4.0 dB,驻波比小于2.4,开关驱动电压为17~20 V。     

Single-VCO multi-band DTV frequency synthesizer with a divide-by-3 frequency divider for quadrature signal generation

A multi-band frequency synthesizer for In-phase and Quadrature (I/Q) LO signal generation in Digital TV tuners is presented. Using divisor numbers other than powers of 2 (2 ⁿ ) for quadrature generation, reduces the required frequency range of the VCO, hence the number of VCO circuits, in multi-band frequency synthesizers. In the proposed synthesizer, VHF, UHF and L-band frequencies are covered with only one VCO. This is achieved by using a novel divide-by-3 circuit which produces precise I/Q LO signals. The VCO tuning range in this design is 2,400–3,632 MHz which is covered by a 6-bit switched-capacitor bank. A fast adaptive frequency calibration block selects the closest VCO frequency to the target frequency by setting the coarse-tuning code prior to the start of phase lock. A programmable charge pump is used to reduce variations in PLL characteristics over the frequency range. The synthesizer has been fabricated in a 0.18 μm CMOS technology and the die area is 1.7 × 1.6 mm². It consumes 27 mA from a 1.8 V power supply. Measurement results show operation of the proposed divide-by-3 circuit over the entire VCO frequency range. The synthesizer quadrature output phase noise for UHF and VHF bands is <−131dBc/Hz at 1.45 MHz offset.     

一种应用于超高频RFID的自干扰抵消电路

提出了一种应用于超高频RFID的集成自干扰抵消电路,它主要由一个6位有源移相器、一个3位可控增益功率放大器和缓冲器组成。有源移相器采用可降位的编码方式,简化了数字逻辑。可控增益功率放大器通过采用电容补偿技术和偏置点的优化选取来提高线性度。该自干扰抵消电路在130 nm CMOS工艺下实现,采用1.5 V和3.3 V双电源供电。后仿真结果显示,针对8 dBm的自干扰信号,该电路在840~940 MHz带宽内的自干扰抑制比大于28 dB。     

A 150-mW, 8-bit video-frequency A/D converter

The authors describe an 8-bit, extremely low-power, flash A/D converter LSI for video-frequency image signal processing. This converter uses a shallow-groove-isolated bipolar VLSI technology. It consumes only 150 mW, which is half the amount of the lowest power consumption so far reported. This low level of power consumption is achieved by the use of a comparator circuit, which is newly designed. This converter can digitize video signals of up to 10 MHz at a conversion rate of 30 MHz. A differential gain (DG) error of 1% and a differential phase (DP) error of less than 0.5/spl deg/ were observed.     

基于加载线型Ka频段的五位数字移相器

数字移相器广泛应用于相控阵雷达中,本文采用一前一后加载支线的方法设计了 11.25°,22.5°和45°移相单元,以3 dB支线耦合器的形式设计90°和180°移相单元,在Ka频段研制出五位数字移相器。该移相器在30 GHz~31 GHz工作频带内,各移相单元实测相移误差最大为6.5°,最小为0.2°;插入损耗最大为11.8 dB,最小为8.6 dB;输入驻波比小于2,整个电路尺寸为110 mm×55 mm×25 mm。