一种提高Power VDMOSFET栅电荷性能的新结构

文章提出一种减小VDMOSFET栅电荷（Qg）的新结构，通过二维数值模拟：相对于常规VDMOSFET，该结构将栅电荷降低42．93％，器件优值（FOM=Qg＊Ron）降低37．05％。我们分析了新结构的主要特性，并与常规VD-MOSFET进行了比较和参数优化分析。     

减小VDMOS密勒电容和反向恢复电荷的研究

提出了在VDMOS FET中减小密勒电容和反向恢复电荷的一种新结构，该结构结合了肖特基接触和分段多晶硅栅的方法。数值分析仿真结果表明，在相同器件单元尺寸下，该结构优于常规VDMOS FET，密勒电容Cgd可减少73．25％，Qgd和导通电阻优值减小65．02％，显示出很好的Qgd*Rds（on）改善性能；同时，反向恢复电荷减少了40．76％。     

高频控制开关用沟槽MOSFET的研究

高频控制开关用功率器件要同时具备极低的导通电阻和栅漏电荷值,从而降低导通损耗和开关损耗.基于器件与工艺模拟软件TsupremⅣ和Medici,研究了工艺参数和设计参数对沟槽MOSFET器件击穿电压、比导通电阻和栅漏电荷的影响,优化设计了耐压30 V的开关用沟槽MOSFET器件.对栅极充电曲线中平台段变倾斜的现象,运用沟道长度调制效应给出了解释.     

栅极下加氧化层的新型沟槽栅E-JFET仿真研究

新结构沟槽栅E-JFET的特点是在栅极下隐埋局域氧化层,以降低栅电容,从而改善器件的开关速度,尤其是适用于低压高频领域。通过理论及仿真分析,与无隐埋氧化层的沟槽栅MOSFET以及沟槽栅E-JFET进行了性能比较。结果证明,该结构具有最低的开关功耗,即Q0最小,在相同条件下相对于沟槽栅MOSFET和沟槽栅E-JFET来说,Q0的改善分别可达到86．3％和13．4％。     

一种快速关断沟槽型SOI LDMOS器件

围绕降低沟槽型SOI LDMOS功率器件的优值,提出了一种新型多栅沟槽 SOI LDMOS器件(MG-TMOS)。与常规沟槽型SOI LDMOS(C-TMOS)器件相比,新型MG-TMOS器件在不牺牲击穿电压的同时,降低了器件开关切换时充放电的栅漏电荷和器件的比导通电阻。这是因为:1) 新型MG-TMOS器件沟槽里的保护栅将器件的栅漏电容转换为器件的栅源电容和漏源电容,大幅度降低了器件的栅漏电荷;2) 保护栅偏置电压的存在使得器件导通时会在沟槽底部形成一层低阻积累层,从而降低器件的导通电阻。仿真结果表明:该新型沟槽型SOI LDMOS器件的优值从常规器件的503.4 mΩ·nC下降到406.6 mΩ·nC,实现了器件的快速关断。     

电荷耦合内透明集电极IGBT设计与仿真北大核心CSCD

针对沟槽型绝缘栅双极型晶体管(IGBT)栅电容较大、开关速度较慢的问题,基于内透明集电极(ITC)技术,将电荷耦合(CC)的思想应用于槽栅IGBT中。采用仿真工具MEDICI对电荷耦合内透明集电极IGBT(CC-ITC-IGBT)的击穿特性、导通特性和开关特性等进行了仿真研究,重点研究了电荷耦合区掺杂浓度和局域载流子寿命控制区(LCLC)载流子寿命对器件性能的影响,并和普通的槽栅内透明集电极IGBT进行了对比。结果表明,在给定的参数范围内,新结构在快速关断区域折中特性曲线更好,在低导通压降区域,优势变得不太明显,因而电荷耦合内透明集电极IGBT更适合做快速关断型。     

功率MOSFET器件栅电荷测试与分析

栅电荷是表征功率MOSFET器件动态特性的重要参数之一,其测试结果与时间和频率有关,受分布参数、测试夹具和电路结构等因素影响较大。其参数直接影响器件整体性能,设计不好将导致器件没使用时已击穿甚至损坏,在军用功率MOSFET器件研制生产和使用验收中列为必测参数。随着对MOSFET器件可靠性要求的不断提高,栅电荷的测试重要性凸显。针对目前国内外栅电荷测试现状及存在的问题做了详尽阐述,为国内的栅电荷测试提供一定的参考和指导。     

多晶硅部分剥离技术对抗辐照VDMOS动态特性的影响

在考虑VDMOS器件的抗辐照特性时,为了总剂量辐照加固的需求,需要减薄氧化层的厚度,然而,从VDMOS器件的开关特性考虑,希望栅氧化层厚度略大些。本文论证了在保证抗辐照特性的需求的薄氧化层条件下,采用漂移区多晶硅部分剥离技术以器件动态特性的可行性,研究了该结构对器件开启电压、击穿电压、导通电阻、寄生电容、栅电荷等参数的影响,重点研究了漂移区多晶硅窗口尺寸对于VDMOS动态特性的影响。模拟结果显示,选取合理的多晶硅尺寸,可以降低栅电荷Qg,减小了栅-漏电容Cgd,减小器件的开关损耗、提高器件的动态性能。     

一种100V分离栅沟槽MOSFET的优化设计北大核心CSCD

把多个侧壁阶梯氧化层应用于分离栅沟槽MOSFET(Split-Gate Trench MOSFET,SGT结构),并把改进的结构称为多阶梯侧壁氧化层分离栅沟槽MOSFET(Multi-Step Sidewall Oxides Split-Gate Trench MOSFET,MSO结构),之后介绍了MSO结构的器件结构和制备工艺,重点借助TCAD仿真软件对MSO结构的外延层掺杂浓度、顶部侧氧厚度与底部侧氧厚度进行优化,最终仿真得到击穿电压为126V,特征导通电阻为30.76mΩ·mm^2和特征栅漏电荷为0.351nC·mm^(-2)的MSO结构.在近似相等的击穿电压下,与传统SGT结构相比,MSO结构的特征导通电阻及特征栅漏电荷均有所降低,这两项参数综合反映器件的优值(FOM=Qgd,sp×RonA)降低了39.6%.     

沟槽栅低压功率MOSFET的发展（上）——减小漏源通态电阻Rds（on）

近些年来,采用各种不同的沟槽栅结构使低压MOSFET功率开关的性能迅速提高。本文对该方面的新发展进行了论述。本文上篇着重于降低通态电阻Rds（on）方面的技术发展,下篇着重于降低优值FOM方面的技术发展。     

Gate-drain charge analysis for switching in power trench MOSFETs

For the switching performance of low-voltage (LV) power MOSFETs, the gate-drain charge density (Q/sub gd/) is an important parameter. The so-called figure-of-merit, which is defined as the product of the specific on-resistance (R/sub ds,on/) and Q/sub gd/ is commonly used for quantifying the switching performance for a specified off-state breakdown voltage (BV/sub ds/). In this paper, we analyzed the switching behavior in power trench MOSFETs by using experiments and simulations, focusing on the charge density Q/sub gd/. The results of this analysis can be used for further optimization of these devices. The results show that the Q/sub d/ can be split into three charge contributions: accumulation, depletion, and inversion charge. It is shown that the inversion charge is located mainly underneath the trench bottom. The accumulation and depletion charge contribute each about 45% in conventional LV trench MOSFETs and can be reduced by using a thick bottom oxide in a shallow trench gate just extending in the drift region. Further, we derived an analytical model for calculating the Q/sub gd/, that takes into account the geometry dependence.     

Resonant gate driver with efficient gate energy recovery and switching loss reduction

This article describes a novel resonant gate driver for charging the gate capacitor of power metal-oxide semiconductor field-effect-transistors (MOSFETs) that operate at a high switching frequency in power converters. The proposed resonant gate driver is designed with three small MOSFETs to build up the inductor current in addition to an inductor for temporary energy storage. The proposed resonant gate driver recovers the CV² gate loss, which is the largest loss dissipated in the gate resistance in conventional gate drivers. In addition, the switching loss is reduced at the instants of turn on and turn off in the power MOSFETs of power converters by using the proposed gate driver. Mathematical analyses of the total loss appearing in the gate driver circuit and the switching loss reduction in the power switch of power converters are discussed. Finally, the proposed resonant gate driver is verified with experimental results at a switching frequency of 1 MHz.     

Lateral power MOSFET for megahertz-frequency, high-density DC/DC converters

DC/DC converters to power future CPU cores mandate low-voltage power metal-oxide semiconductor field-effect transistors (MOSFETs) with ultra low on-resistance and gate charge. Conventional vertical trench MOSFETs cannot meet the challenge. In this paper, we introduce an alternative device solution, the large-area lateral power MOSFET with a unique metal interconnect scheme and a chip-scale package. We have designed and fabricated a family of lateral power MOSFETs including a sub-10 V class power MOSFET with a record-low R/sub DS(ON)/ of 1m/spl Omega/ at a gate voltage of 6V, approximately 50% of the lowest R/sub DS(ON)/ previously reported. The new device has a total gate charge Q/sub g/ of 22nC at 4.5V and a performance figures of merit of less than 30m/spl Omega/-nC, a 3/spl times/ improvement over the state of the art trench MOSFETs. This new MOSFET was used in a 100-W dc/dc converter as the synchronous rectifiers to achieve a 3.5-MHz pulse-width modulation switching frequency, 97%-99% efficiency, and a power density of 970W/in/sup 3/. The new lateral MOSEFT technology offers a viable solution for the next-generation, multimegahertz, high-density dc/dc converters for future CPU cores and many other high-performance power management applications.     

The future of power semiconductor device technology

Power electronic systems have benefited greatly during the past ten years from the revolutionary advances that have occurred in power discrete devices. The introduction of power metal-oxide-semiconductor field-effect transistors (MOSFETs) in the 1970s and the insulated gate bipolar transistors (IGBTs) in the 1980s enabled design of very compact high-efficiency systems due to the greatly enhanced power gain resulting from the high input impedance of these structures. Recently, significant improvements in the performance of silicon-power MOSFETs has been achieved by using innovative vertical structures with charge coupled regions. Meanwhile, silicon IGBTs continue to dominate the medium- and high-voltage application space sue to scaling of their voltage ratings and refinements to their gate structure achieved by using very large scale integration (VLSI) technology and trench gate regions. Research on a variety of MOS-gated thyristors has also been conducted, resulting in some promising improvements in the tradeoff between on-state power loss, switching power loss, and the safe-operating-area. Concurrent improvements in power rectifiers have been achieved at low-voltage ratings using Schottky rectifier structures containing trenches and at high-voltage ratings using structures that combine junction and Schottky barrier contacts. On the longer term, silicon carbide Schottky rectifiers and power MOSFETs offer at least another tenfold improvement in performance. Although the projected performance enhancements have been experimentally demonstrated, the defect density and cost of the starting material are determining the pace of commercialization of this technology at present     

Characterization of P-channel power trench MOSFETs with polycrystalline silicon germanium gate electrode for faster switching

Electrical switching characteristics using polycrystalline silicon–germanium (poly-Si_l?xGe_x) gate for P-channel power trench MOSFETs was investigated. Switching time reduction of over 22% was observed when the boron-doped poly-Si gate was replaced with a similarly boron-doped poly-SiGe gate on the P-channel power MOSFETs. The fall time (T_f) on MOSFETs with poly-SiGe gate, was found to be ～11 ns lesser than the poly-Si gate MOSFET which is ～60% improvement in switching performance. However, all the switching improvement was observed during the fall times (T_f). The reason could be the higher series resistance in the switching test circuit masking any reduction in the rise times (T_r). Faster switching is achieved due to a lower gate resistance (R_g) offered by the poly-SiGe gate electrode as compared to poly-silicon (pSi) material. The pSi gate resistance was found to be 6.25 Ω compared to 3.75 Ω on the poly-SiGe gate measured on the same device. Lower gate resistance (R_g) also means less power is lost during switching thereby less heat is generated in the device. A very uniform boron doping profile was achieved with-in the pSiGe gate electrode, which is critical for uniform die turn on and better thermal response for the power trench MOSFET. pSiGe thin film optimization, properties and device characteristics are discussed in details in the following sections.     

超薄栅n-MOSFETs热载流子寿命预测模型

对氧化层厚度为 4和 5 nm的 n- MOSFETs进行了沟道热载流子应力加速寿命实验 ,研究了饱和漏电流在热载流子应力下的退化 .在饱和漏电流退化特性的基础上提出了电子流量模型 ,此模型适用于氧化层厚度为 4— 5 nm或更薄的器件     

Suppression of Dynamic On-Resistance Increase and Gate Charge Measurements in High-Voltage GaN-HEMTs With Optimized Field-Plate Structure

The dynamic on-resistance increase associated with the current collapse phenomena in high-voltage GaN high-electron-mobility transistors (HEMTs) has been suppressed by employing an optimized field-plate (FP) structure. The fabricated GaN-HEMTs of 600 V/4.7 A and 940 V/4.4 A for power-electronics applications employ a dual-FP structure consisting of a short-gate FP underneath a long-source FP. The measured on-resistance shows minimal increase during high-voltage switching due to increased electric-field uniformity between the gate and drain as a result of using the dual FP. The gate-drain charge Q _gd for the fabricated devices has also been measured to provide a basis for discussion of the ability of high-speed switching operation. Although Q _gd /A (A: active device area) was almost the same as that of the conventional Si-power MOSFETs, R _on A was dramatically reduced to about a seventh of the reported 600-V Si-MOSFET value. Therefore, R _on Q _gd for 600-V device was reduced to 0.32 OmeganC, which was approximately a sixth of that for the Si-power MOSFETs. The high-voltage GaN-HEMTs have significant advantages over silicon-power MOSFETs in terms of both the reduced on-resistance and the high-speed switching capability.     

Impact of the gate driver voltage on temperature sensitive electrical parameters for condition monitoring of SiC power MOSFETs

Condition monitoring using temperature sensitive electrical parameters (TSEPs) is widely recognized as an enabler for health management of power modules. The on-state resistance/forward voltage of MOSFETs, IGBTs and diodes has already been identified as TSEPs by several researchers. However, for SiC MOSFETs, the temperature sensitivity of on-state voltage/resistance varies depending on the device and is generally not as high as in silicon devices. Recently the turn-on current switching rate has been identified as a TSEP in SiC MOSFETs, but its temperature sensitivity was shown to be significantly affected by the gate resistance. Hence, an important consideration regarding the use of TSEPs for health monitoring is how the gate driver can be used for improving the temperature sensitivity of determined electrical parameters and implementing more effective condition monitoring strategies. This paper characterizes the impact of the gate driver voltage on the temperature sensitivity of the on-state resistance and current switching rate of SiC power MOSFETs. It is shown that the temperature sensitivity of the switching rate in SiC MOSFETs increases if the devices are driven at lower gate voltages. It is also shown, that depending on the SiC MOSFET technology, reducing the gate drive voltage can increase the temperature sensitivity of the on-state resistance. Hence, using an intelligent gate driver with the capability of customizing occasional switching pulses for junction temperature sensing using TSEPs, it would be possible to implement condition monitoring more effectively for SiC power devices.     

Gate-resistance-limited switching frequencies of power MOSFETs

High-frequency switching limitation of a power MOSFET resulting from large gate resistance is studied. It is shown that a maximum gate switching frequency can be identified to minimize resistive power dissipation in the gate. Power MOSFETs with refractory silicide gates are shown to result in more than a fivefold improvement in this frequency compared to conventional heavily POCl₃-doped polysilicon-gated MOSFETs with metal gate runners