通孔电镀填孔工艺研究与优化

为了提高高密度互连印制电路板的导电导热性和可靠性,实现通孔与盲孔同时填孔电镀的目的,以某公司已有的电镀填盲孔工艺为参考,适当调整填盲孔电镀液各组分浓度,对通孔进行填孔电镀。运用正交试验法研究加速剂、抑制剂、整平剂、H2SO4浓度对通孔填充效果的影响,得到电镀填通孔的最优参数组合,并对其可靠性进行测试。将得到的最优电镀配方用于多层板通孔与盲孔共同填孔电镀。结果表明:电镀液各成分对通孔填充效果的影响次序是:抑制剂>整平剂>加速剂>H2SO4;最优配方是:加速剂浓度为0.5 ml/L,抑制剂浓度为17 ml/L,整平剂浓度为20ml/L,H2SO4浓度为30 g/L。在最优配方下,通孔填孔效果显著提高,其可靠性测试均符合IPC品质要求。该电镀配方可以实现多层板通孔与盲孔共同填孔电镀,对PCB领域具有实际应用价值。     

微导通孔填铜电镀的影响因素研究

由于印制电路板对高密度、高精度、高可靠性及低成本的强烈需求,常规的导通孔敷形镀技术已经不能满足高密度布线的要求,所以提出了微导通孔填铜电镀和微盲孔填铜电镀技术。通过在添加剂方面对影响微导通孔填铜电镀的因素进行分析,运用正交试验的研究方法,得到了添加剂的最优组合和配比,从而实现微导通孔的较好填充。     

提高电镀填盲孔效果的研究

随着电子产品的持续发展,HDI印制电路板的应用越来越广泛,本文通过正交实验优化电镀填孔工艺参数,并通过控制变量法研究了通孔孔径及位置对盲孔电镀填孔效果的影响,并以金相显微镜分析盲孔的凹陷度作为考察指标。研究结果表明采用优化参数能够降低盲孔填充凹陷度,通孔对盲孔的填孔电镀效果会产生影响,随着通孔孔径的增大,对盲孔的填孔电镀越有利,同时实验还发现,若在孔金属化后通孔孔壁与盲孔底部铜层电导通有利于盲孔的填孔。     

LTCC互连基板金属化孔工艺研究

LTCC基板互连金属化孔工艺技术是低温共烧陶瓷工艺过程中的关键技术,它直接影响陶瓷基板的成品率和可靠性。文章从影响互连金属化孔的因素出发,介绍了金属化通孔填充工艺及控制技术、金属化通孔材料热应力的影响、金属化通孔材料收缩率的控制等三方面技术,并给出了如下的解决方案。采用合适的通孔填充工艺技术和工艺参数;合理设计控制通孔浆料的收缩率和热膨胀系数,使通孔填充浆料与生瓷带的收缩尽量一致,以便降低材料的热应力;金属化通孔烧结收缩率的控制可以通过导体层的厚度、烧结曲线与基板烧结收缩率的关系、叠片热压的温度和压力等方面来实现。     

5G功放板填孔覆盖镀层耐热性能研究

5G功放板覆盖镀层（POFV）的耐热性能直接影响印制线路板（PCB）组装之后的可靠性，因此在制作此类产品之前，重点对5G功放板填孔POFV的耐热性能的影响因子进行了研究。通过采用鱼骨图对影响因子进行梳理，找出关键的流程及影响因子，针对性对印制线路板制作的树脂填孔流程的树脂烤板参数、电镀通孔（PTH）流程除胶参数、在流程中的停留时间，以及填孔树脂本身的热膨胀（CTE）特性等影响因子进行对比实验，并对各测试结果进行总结分析。根据实验测试结果，确认了影响填孔覆盖镀层与树脂分离的主要因素是所选填孔树脂与基板CTE特性的匹配性，此外填孔后的树脂固化烤板参数、磨树脂后到电镀通孔的停留时间、电镀通孔过程中除胶条件等对POFV镀层与填孔树脂分离有少许影响。     

双面印制电路的印刷、吸附、催化加成法制备工艺

开发出了一种双面印制电路板的加成法制备工艺,其具体流程包括：（1）在基板上需要双面导通的部位钻孔,并浸涂离子吸附功能油墨;（2）在基板双面印刷掩膜,暴露出线路图形与通孔部位;（3）基板浸入硝酸银溶液中,吸附银离子至图形和通孔表面;（4）除去掩膜,使用化学镀铜的方法使表面线路和通孔金属化,得到所需双面印制电路板。本工艺可以将双面印制电路线路和通孔一步加成制造,简化了工序,降低了成本,节约了材料。     

低温共烧陶瓷多层基板精细互连技术

微电子技术和封装工艺的发展使超大规模集成电路(VLSI)的密度越来越高,而高密度低温共烧陶瓷(LTCC)基板的制作依赖于基板内部导体的精细互连技术.为了满足LTCC多层基板高密度互连的工艺要求,必须使基板微通孔的直径及导线线宽缩小到100 μm以内.基于此,首先介绍了LTCC生瓷带层的微通孔形成与填充工艺,以及所形成的微通孔的特点;利用厚膜丝网印刷技术形成精细导线,分析了影响印刷质量的工艺参数;最后简要介绍了薄膜光刻等新技术.通过应用上述几种先进的精细互连工艺技术,极大地提高了LTCC多层基板的互连密度.     

硅通孔电镀铜填充工艺优化研究

研究了孔径40μm的硅通孔铜电镀填充工艺,通过改善电镀工艺条件使得孔径40μm、孔深180μm的硅通孔得以填充满。首先,在种子层覆盖以及电镀液相同条件下通过改变电镀电流密度,研究不同电流密度对于铜填充的影响,确定优化电流密度为1ASD(ASD:平均电流密度)。之后,在相同电流密度下,详细分析了超声清洗、去离子水冲洗以及真空预处理等电镀前处理工艺对铜填充的影响。实验表明,采用真空预处理方法能够有效的将硅通孔内气泡排出获得良好的铜填充。最终铜填充率在电流密度为1ASD、真空预处理条件下接近100%。     

全铜通孔柔性LED封装热学性能仿真分析

柔性基板封装(COF)是一种新型LED封装形式。本研究在柔性基板中的高分子绝缘层(PI)中添加全铜通孔,通过有限元仿真分析全铜通孔对LED封装热学性能的影响。研究结果表明：在柔性LED封装中,PI层热阻最大,是导致芯片结温高的主要因素。PI层中全铜通孔的添加使PI层热阻大幅降低,显著提升LED封装的垂直散热能力。基于仿真计算结果,建立了PI层中添加全铜通孔数量与LED封装热阻间的对应关系。针对本研究中的封装结构,采用8*8 的全铜通孔阵列对LED封装的热学性能提升效果显著。     

硅通孔尺寸与材料对热应力的影响

通过有限元分析研究了单个硅通孔及两片芯片堆叠模型的热应力。采用单个硅通孔模型证实了应力分布受填充材料(铜,钨)的影响,提出钨在热应力方面的优越性,确定了硅通孔尺寸(通孔直径、深宽比等因素)与热应力大小间的对应关系。为寻找拥有最佳热应力的材料组合,采用两片芯片堆叠的二维模型,对常用材料的组合进行了仿真分析,发现以二氧化硅为隔离层,钨为填充金属,锡为键合层的模型具有最理想的热应力特性,此外,铜、ABF以及锡的组合也表现出良好的热应力特性。     

HDI板盲孔盘无铜探讨

埋盲孔常规PcB走向更高密度的HDI／BuM板的必由之路,传统PCB板导孔难以胜任其基层（a＋n＋b,nN芯板的层数,a和b为高密度积层的层数）的层数越来越多结构产品,必须运用仅在需要电气互连的相关的内层之间才有导通孔的埋／盲孔进行导通;而盲孔品质直接关系产品导通性能;文章根据我司出现盲孔焊盘无铜现象进行理论分析,通过对PCB板从问题分析、过程、影响的因素几个方面进行了详细的分析。最后对如何在生产过程中进行管理给出了建议。     

A modifying algorithm of the topological VLSI layer by dummy filling features based on modeling the chemical-mechanical planarization

The approach to modeling chemical-mechanical planarization (CMP) based on the notion of the effective filling density, which makes it possible to calculate the thickness distribution of the interlayer dielectric (ILD) on the surface of the VLSI crystal, is considered. The polynomial CMP model previously proposed in [1] is compared to model [2]. The algorithm of modifying the pattern of the VLSI topological layer by the dummy filling features, which was proposed in [3], is described using the proposed polynomial model. The results of model investigations of applying the developed modification algorithm of topological layers by examples of various VLSI types are presented.     

Problems of PCB microvias filling by conductive paste

The using of conductive paste for the through holes and the blind holes filling in PCBs were analyzed. Such processes seem to be easy and can be applied instead of common used electrochemical plating process. The performed investigations have shown that these processes are not so simple.To understand more problems connected with microvias filling, the influence of adhesive rheology and printing parameters for the quality of small diameter through holes filling and small diameter blind vias were investigated. The performed analysis was supplemented by electrical measurements as well as observation of microvia cross sections. The FR-4 laminate test samples with through holes with 0.3, 0.5 and 0.8 mm diameters as well as blind holes diameters 0.15, 0.3 and 0.45 mm were used in experiments.The average single fills resistances in the range 50 mΩ for through hole fillings diameter 0.5 mm and below 20 mΩ for blind holes diameter 0.3 mm was obtained. The adhesive fill resistance is stable after dump heat and thermal cycling tests.     

以石墨为导电基质的黑孔化新技术

介绍了以石墨作为导电基质,进行印刷电路板孔金属化直接电镀的黑孔新技术,探讨了以石墨分散液在孔壁成膜的过程与导电原理。介绍了黑孔处理的工艺流程,以及黑孔质量与黑孔液稳定性的检测方法。通过孔横截面的金相显微照片确认了通孔与盲孔经过以石墨为导电基质的黑孔液处理后,均能获得完整的电镀铜层。     

Multilayer planarization of polymer dielectrics

Polymers are widely used in the microelectronics industry as thin-film interlevel dielectrics layers between metal lines, as passivation layers on semiconductor devices and in various packaging applications. As multiple layers of polymer and patterned metal are constructed, the ability of these polymers to planarize topographical features becomes increasingly important. In this study, the degree of planarization (DOP) for five commercially available polymers has been examined for three different structural configurations with the intent of simulating practical applications. Specifically, this study investigates single layer planarization, multiple coat planarization, and planarization of metal lines patterned on a polymer base. This study also examines the effects of orientation of the metal structure to polymer flow during spin casting and location on the wafer. The polymers are selected to investigate different polymer chemistries frequently used in the microelectronics industry. The underlying structures were fabricated using standard photolithography and electroplating techniques. Feature dimensions include 25-200 μm line spacings and widths with the polymer overcoat thickness being twice the height of the underlying structures     

低损耗正方晶格微结构光纤的设计

应用多极法对正方晶格微结构光纤的损耗特性进行了数值模拟,研究了包层各层空气孔直径和包层空气孔层数在1.31 μm和1.55 μm处对损耗特性的影响.研究发现,通过选择高空气填充率的结构参数可以有效地降低光纤的损耗;通过增大最外层空气孔的直径或包层空气孔层数,可在保持色散特性不变的基础上显著降低光纤的损耗.文章的计算和分析可以为设计适当色散特性的低损耗微结构光纤提供理论依据.     

工作在1550nm的全固态光子晶体光纤的设计

利用全矢量平面波展开法对三角形排布孔包层-圆纤芯结构的光子晶体光纤的光子带隙特性进行了数值模拟,对比研究了传统光子晶体光纤(空气-石英纤芯结构)和全固态光子晶体光纤(非空气-石英纤芯结构)的光子带隙(导模)与结构参数(包层孔直径dclh、包层孔间距和包层孔填充比f)的关系,设计出了一组合适的结构参数(纤芯直径dco＝5.3 m,包层孔材料的折射率nclh=1.65,dclh＝1.0 m,＝2.0 m,f＝0.7),可以使相应的全固态光子晶体光纤工作在1 550 nm的现代光通信波长上,且光子带隙可以达100 nm.     

Intermodal interference based refractive index sensor employing elliptical core photonic crystal fiber

A refractive index (RI) sensor based on elliptical core photonic crystal fiber (EC-PCF) has been proposed. The asymmetric elliptical core introduces the polarization-dependent characteristics of the fiber core modes. The performances of intermodal interference between the intrinsic polarization fiber core modes are investigated by contrast in two interferometers based on the Mach-Zehnder (M-Z) and Sagnac interference model. In addition, the RI sensing characteristics of the two interferometers are studied by successively filling the three layers air holes closest to the elliptical core in the cladding. The results show that the M-Z interference between LP01 and LP11 mode in the same polarized direction is featured with the incremental RI sensing sensitivity as the decreasing interference length, and the infilled scope around the elliptical core has a weak correlation with the RI sensing sensitivity. Due to the high birefringence of LP11 mode, the Sagnac interferometer has better RI sensing performance, the maximum RI sensing sensitivity of 12 000 nm/RIU is achieved under the innermost one layer air holes infilled with RI matching liquid of RI=1.39 at the pre-setting EC-PCF length of 12 cm, which is two orders of magnitude higher than the M-Z interferometer with the same fiber length. The series of theoretical optimized analysis would provide guidance for the applications in the field of biochemical sensing.     

Spin-on films add new dimension to ULSI circuits

Spin-on oxide films, natural candidates for improving interlevel dielectric planarization in ULSI circuits, are reviewed. The spin-on process, one in which a thin film is produced by spin-casting a liquid on a rotating wafer, is described. Spin-on films combine the planarization capabilities of a fluid with the dielectric properties of an oxide. They fill all the lower regions over the wafer and produce a planar top layer. Spin-on insulators can be used in combination with chemically-vapor-deposited (CVD) materials, and can also be combined with an etchback step to improve planarization. As a result, the depths of vias in the etching process can be made more uniform, and voids in the filling of via-contacts, which become a significant problem as the via size shrinks, can be eliminated     

Dependence of Dye Regeneration and Charge Collection on the Pore‐Filling Fraction in Solid‐State Dye‐Sensitized Solar Cells

Solid‐state dye‐sensitized solar cells rely on effective infiltration of a solid‐state hole‐transporting material into the pores of a nanoporous TiO₂ network to allow for dye regeneration and hole extraction. Using microsecond transient absorption spectroscopy and femtosecond photoluminescence upconversion spectroscopy, the hole‐transfer yield from the dye to the hole‐transporting material 2,2′,7,7′‐tetrakis(N,N‐di‐p‐methoxyphenylamine)‐9,9'‐spirobifluorene (spiro‐OMeTAD) is shown to rise rapidly with higher pore‐filling fractions as the dye‐coated pore surface is increasingly covered with hole‐transporting material. Once a pore‐filling fraction of ≈30% is reached, further increases do not significantly change the hole‐transfer yield. Using simple models of infiltration of spiro‐OMeTAD into the TiO₂ porous network, it is shown that this pore‐filling fraction is less than the amount required to cover the dye surface with at least a single layer of hole‐transporting material, suggesting that charge diffusion through the dye monolayer network precedes transfer to the hole‐transporting material. Comparison of these results with device parameters shows that improvements of the power‐conversion efficiency beyond ≈30% pore filling are not caused by a higher hole‐transfer yield, but by a higher charge‐collection efficiency, which is found to occur in steps. The observed sharp onsets in photocurrent and power‐conversion efficiencies with increasing pore‐filling fraction correlate well with percolation theory, predicting the points of cohesive pathway formation in successive spiro‐OMeTAD layers adhered to the pore walls. From percolation theory it is predicted that, for standard mesoporous TiO₂ with 20 nm pore size, the photocurrent should show no further improvement beyond an ≈83% pore‐filling fraction.