一种基于时延配置表的FPGA静态时序分析算法

为减小现场可编程门阵列(FPGA)关键路径的延时误差,提出一种基于时延配置表的静态时序分析算法。算法建立了一种基于单元延时与互连线延时配置表的时延模型。该模型考虑了工艺角变化对延时参数的影响,同时在时序分析过程中,通过分析路径始节点与终节点的时钟关系,实现了复杂多时钟域下的路径搜索与延时计算。实验结果表明,与公认的基于查找表的项目评估技术(PERT)算法和VTR算法相比,关键路径延时的相对误差平均减少了8.58%和6.32%,而运行时间平均仅增加了19.96%和9.59%。     

考虑多输入跳变的STA伪关键路径识别算法

通过在当前静态时序分析(STA)中引入多输入跳变(MIT)参数库和布尔可满足方法,提出了一种考虑多输入跳变的静态时序分析伪关键路径识别算法。实验结果表明,与传统的静态时序分析算法相比,该算法能识别50%的伪关键路径,并且真实关键路径延时平均减少14.67%,提高了真实关键路径延时边界预估的精确性。     

微处理器设计中的时序验证及优化

为了解决微处理器设计中时序验证和性能优化问题,采取可综合代码设计到静态时序分析过程中针对关键路径进行处理的策略,完成了系统性能优化的完整流程。理论分析和实践结果证明,根据RTL级的静态时序分析结果进行系统关键路径的优化,可显著提高微处理器的总体性能,减少设计的迭代次数,缩短了设计的周期。     

技术资源

高档ASIC设计的时序分析和验证 Mentor Graphics公司的SST Velocity是静态时序分析工具,在验证设计时,它对整个ASIC进行门级静态时序分析。它和现有设计流程一致,仍然可以利用现的有静态时序分析方案。设计者可以确定关键路径,进行备用区和时钟树分析。它可用于进行布局前和布局后的时序验证,并支持VHDL、Verilog和EDIF网络列表格式和SDF时序后标注文件。SST Velocity可验证具有复杂时钟结构或多级异步时钟域的设计。它还能定位关键路径,进行备用区和时钟树分析,并可以自动地消除常见的虚假路径,即那些因为一个门的边输入为常量而不会传播信号的路径,或总线环路经。SST Velocity允许设     

基于神经网络的逻辑门NBTI退化建模与计算

提出了基于神经网络的逻辑门退化延迟模型。根据逻辑门延迟数据特征,采用神经网络BP算法,对仿真样本数据进行训练,获得7种基本逻辑门延迟退化计算方法以及网络模型参数。基于45 nm CMOS工艺进行验证,模型计算值与Spice仿真数据的误差不超过5%。在此基础上,提出NBTI效应下的电路路径延迟退化计算流程,并编写计算程序,对基本逻辑门构成的任意组合逻辑电路(ISCAS85)进行NBTI退化分析,获得路径时序的NBTI退化量。采用该模型,可在电路设计阶段预测电路时序,为高性能、高可靠性数字集成电路的设计提供重要依据。     

电路抗老化设计中基于门优先的关键门定位方法

随着CMOS工艺尺寸不断缩小,尤其在65 nm及以下的CMOS工艺中,负偏置温度不稳定性(NBTI)已经成为影响CMOS器件可靠性的关键因素。提出了一种基于门优先的关键门定位方法,它基于NBTI的静态时序分析框架,以电路中老化严重的路径集合内的逻辑门为优先,同时考虑了门与路径间的相关性,以共同定位关键门。在45 nm CMOS工艺下对ISCAS基准电路进行实验,结果表明:与同类方法比较,在相同实验环境的条件下,该方法不仅定位关键门的数量更少,而且对关键路径的时延改善率更高,有效地减少了设计开销。     

基于MCMM技术快速实现IC时序收敛

如今的集成电路(Integrated Circuit,IC)设计往往要求芯片包含多个工作模式,并且在不同工艺角(corner)下能正常工作。工艺角和工作模式的增加,无疑使时序收敛面临极大挑战。本文介绍了一种在多工艺角多工作模式下快速实现时序收敛的技术——MCMM(Multicorner-Multimode)技术,该技术将工艺角和模式进行组合,对时序同时进行分析和优化,到达快速实现时序收敛的目的。该技术应用于一个80万门基于TSMC 0.152μm logic工艺的电力网载波通信(PLC)芯片设计,设计实例表明,利用MCMM技术不但可以解决时序难以收敛的问题,而且大大降低了芯片设计周期。     

基于时间窃取的数字电路时序优化方法

在大规模数字集成电路设计中,时序分析是签核(Signoff)的关键一环,目前电路设计中主要通过关键路径优化使电路时序达到要求,但这类方法可能会使电路结构发生改变,电路版图也要进行大量更改,延长了芯片设计周期.为能快速解决电路时序修正问题,提出了一种基于动态电路设计思想的时移触发器,此触发器去除了建立(Setup)时间,基于SMIC40 nm工艺完成电路设计和仿真,进行了触发器标准单元版图绘制,通过合理分配参数,时序参数优于标准单元库中的D触发器.不同工艺角(Process,Voltage,Temperature,PVT)仿真表明,在典型情况下,时移触发器相比于SMIC40 nm标准单元库中相同驱动能力的D触发器输出响应时间加速比达到188.6%.结合所设计的时移触发器和时间窃取(Timing Borrow)方法,分析了数字电路中时序分配情况,所设计的触发器可应用于工程更改计划(Engineering Change Order,ECO)阶段进行数字电路时序修复和优化,可减少时钟树和逻辑电路调整,有效缩短数字电路芯片设计周期.     

高速桶式移位器的设计研究

文章基于传统的部分译码桶式移位器,对其关键路径进行了改进,根据移位的特点,引进了一种逆序变换方法以达到数据路径与控制路径的平衡,并据此提出了一种折叠式的电路结构以减少连线延迟和面积,改进后BS的关键路径由一级三输入与非门和一级缓冲器组成,实现高速桶式移位器设计。用SMIC0.13!m/1.2V工艺仿真结果显示新结构的桶式移位器的关键路径延迟为0.5ns,比传统结构延迟时间缩短了38%。     

超大规模集成电路中基于OCV的时序收敛方法

当芯片设计进入深亚微米,片上工艺偏差(OCV)造成的时序不确定性,成为超大规模集成电路时序收敛中的关键问题,单纯使用传统时序分析方法,已不能完全达到时序收敛的要求。文中首先介绍了静态时序分析方法,阐述了深亚微米下OCV分析对时序收敛的重要性,并提出对OCV问题建模和分析的方法。最后通过一个具体的设计实例,运用基于OCV的时序分析方法达到时序收敛。     

浮点乘加部件中三操作数前导1预测算法的设计

提出了一种应用于高效浮点乘加部件的三操作数前导1预测算法。高效浮点乘加部件需要买现三个操作数的前导1预测（LOP）电路，传统的LOP算法不能直接处理三个操作数，通过间接方法实现又会增加关键路径延时并增大电路面积。三操作数LOP算法是针对传统LOP算法的这一局限提出的，可以有效缩短前导1预测电路的延时并减少面积．从而缩短整个乘加部件的延时。文章以龙芯2号通用CPU中浮点乘加部件的106位前导1预测电路为例．分别采用传统LOP算法和三操作数LOP算法实现了电路，实验结果表明，三操作数LOP算法比传统算法延时能降低约16．67％．总面积减少约19．63％。     

Crosstalk noise reduction in synthesized digital logic circuits

As CMOS technology scales into the deep submicrometer regime, digital noise is becoming a metric of importance comparable to area, timing, and power, for analysis and design of CMOS VLSI systems. Noise has two detrimental effects in digital circuits: First, it can destroy logical information carried by a circuit net. Second, it causes delay uncertainty: Non critical paths might become critical because of noise. As a result, circuit speed becomes limited by noise, primarily because of capacitive coupling between wires. Most design approaches address the crosstalk noise problem at the layout generation stage, or via postlayout corrections. With continued scaling, too many circuit nets require corrections for noise, causing a design convergence problem. This work suggests to consider noise at the gate-level netlist generation stage. The paper presents a simplified analysis of on-chip crosstalk models, and demonstrates the significance of crosstalk between local wires within synthesized circuit blocks. A design flow is proposed for automatically synthesizing CMOS circuits that have improved robustness to noise effects, using standard tools, by limiting the range of gate strengths available in the cell library. The synthesized circuits incur a penalty in area/power, which can be partially recovered in a single postlayout corrective iteration. Results of design experiments indicate that delay uncertainty is the most important noise-related concern in synthesized static CMOS logic. Using a standard synthesis methodology, critical path delay differences up to 18% of the clock cycle time have been observed in functional blocks of microprocessor circuits. By using the proposed design flow, timing uncertainty was reduced to below 3%, with area and power penalties below 20%.     

Synthesis of representative critical path circuits considering BEOL variations for deep sub-micron circuits

The proportion of interconnect delay in the critical path on a chip is increasing and becomes over 20% in sub-10nm technologies, which means in order to capture post-Si performance accurately, the representative critical path circuit should reflect not only FEOL (front-end-of-line) but also BEOL (back-end-of-line) variations. Since the number of BEOL metal layers exceeds ten and the layers have variation on resistance and capacitance intermixed with resistance variation on vias between them, a very high dimensional design space exploration is necessary to synthesize a representative critical path circuit which is able to provide an accurate performance prediction. To this end, we propose a BEOL-aware methodology of synthesizing a representative critical path circuit, which is able to incrementally explore, starting from an initial path circuit on the post-Si target circuit, routing patterns (i.e., BEOL reconfiguring) as well as gate resizing on the path circuit. Precisely, our synthesis framework of critical path circuit integrates a set of novel techniques: (1) extracting and classifying BEOL configurations for lightening design space complexity, (2) formulating BEOL random variables for fast and accurate timing analysis, and (3) exploring alternative (ring oscillator) circuit structures for extending the applicability of our work. In summary, our synthesis framework is able to reduce the prediction error by 54% and 19% on average over that using the conventional critical path replica and using the conventional method exploiting gate sizing only, respectively.     

Efficient logic-level timing analysis using constraint-guidedcritical path search

As the operating speed of digital circuits dramatically increases with the advance of VLSI technology, it is becoming more critical to ensure that the circuits are free from timing-related design errors. In a traditional static timing approach nonfunctional paths cannot be distinguished from functional ones since the functionality of a circuit is ignored. This often results in overestimation of circuit delay and can degrade the circuit performance. In today's design methodology where the use of automated logic synthesis and module-based design are popular, circuits with a very large number of nonfunctional (false) paths are common. This paper describes an efficient logic-level timing analysis approach that can provide an accurate delay estimate of a digital circuit which may have many long false paths. By using logic incompatibilities in a circuit as constraints for critical path search, the algorithm determines the longest sensitizable path without explicit path enumeration. Since the number of false paths that can be implicitly eliminated is potentially exponential to the number of path constraints, performance improvement is significant     

FLINT+: A runtime-configurable emulation-based stochastic timing analysis framework

ASICs for Stochastic Computing conditions are designed for higher energy-efficiency or performance by sacrificing computational accuracy due to intentional circuit timing violations. To optimize the stochastic behavior, iterative timing analysis campaigns have to be carried out for a variety of circuit timing corner cases. However, the application of common event-driven logic simulators usually leads to excessive analysis runtimes, increasing design time for hardware developers. In this paper, a gate-level netlist-oriented FPGA-based timing analysis framework is proposed, offering a runtime-configuration mechanism for emulating different timing corner cases in hardware without requiring multiple FPGA bitstreams. Logic gates are instrumented with a quantization-based delay model and a critical path selection algorithm is used to reduce the FPGA resource overhead. For an exemplary design space exploration of stochastic CORDIC units, speed-up factors of up to 48 for 10 ps or 476 for 100 ps timing quantization are achieved while maintaining timing behavior deviations lower than 1.5% or 4% to timing simulations, respectively.     

Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision Problems

Debugging and speed-binning a fabricated design requires a pattern-dependent timing model to generate patterns, which static timing analysis is incapable of providing. To address these issues, we propose a timing analysis tool that integrates a pattern-dependent delay model into its analysis. Our approach solves for the delay by using the concept of circuit unrolling and formulation of timing questions as decision problems for input into a satisfiability (SAT) solver. We generate a critical path and input vectors that stimulate it, taking into account pattern-dependent effects such as data-dependent gate delays and multiple-inputs switching. The effectiveness and validity of the proposed methodology is illustrated through experiments on various benchmark circuits and comparisons directly with SPICE.     

Reducing process variation impact on replica-timed static random access memory sense timing

The read access delay of a static random access memory (SRAM) is dominated by the time required to develop a voltage differential on the bit-lines, particularly for small, fast level-1 (L1) caches in microprocessors. For a robust design, the bit-lines must develop a differential sufficient to overcome mismatch due to sense amplifier offsets and other signal path components before the data is sensed. This must be accomplished across all process skews and voltages. This paper proposes a design and optimization technique to minimize the bit-line voltage differential variation across process corners and voltages, which increases the read frequency by reducing the delay guard-band required at the design process corner. The technique reduces the required timing guard-band by minimizing the effects of process variation on the circuit delays. On a 90 nm high-performance cache memory data array, the typical corner guard-band required to generate the differential is reduced by 78%. Total variation in bit-line differential is reduced from 243 to 45 mV across process and voltage corners.     

Mass characterisation of organic transistors and Monte-Carlo circuit simulation

We present a method for designing organic circuits using Monte-Carlo based circuit simulation. The organic devices suffer from mismatch and variations that are due to systematic and random fluctuations in the process and material characteristics. In this work, we have used the variable range hopping model to extract the model parameters using a mass characterisation technique. The parameter fluctuations of organic transistors are taken into account and process corners determined based on static (noise margin) and transient (delay) characteristics. Thus a methodology is developed to find the parameter range of individual devices, within which the circuits are having good performance, for instance inverters working with desired noise margin. We also found out the critical parameters of the transistor, that predominantly affects the static and transient performance of an inverter. These critical parameters can be provided as input to the process engineers to fine tune the process. This information can also be used in developing robust circuit design techniques, which can overcome the variation effects of these critical parameters. Thus, a mass characterisation of transistors combined with the proposed method, allows robust circuit design in the presence of huge process variations.