一种快速瞬态响应无输出电容LDO的研究与设计

设计了一种基于自适应偏置放大器的具有快速瞬态响应的无输出电容LDO.自适应偏置放大器在发生负载瞬态响应时能够调节自身偏置电流以提供较大的输出电流来增加摆率;瞬态响应提升电路通过减小负载电容充放电电流而减小了输出电压的建立时间;通过并联反馈补偿来提高环路的稳定性.仿真结果表明,所设计的无输出电容LDO最大输出电流200mA,最小跌落电压200mV,静态电流仅16μA,全负载正负阶跃变化响应时间分别为2.5μs和3.5μs.     

增强升压型DC-DC瞬态响应的电路设计

设计了一种增强升压型DC-DC转换器瞬态响应电路,该电路通过检测负载跳变条件下输出电压的变化,调节误差放大器的跨导和补偿电阻,提高升压DC-DC转换器环路带宽,加快系统的瞬态响应。同时将该电路应用于一款输入电压＜至1.4 V,输出电压2.5～6.5 V的同步升压型DC-DC转换器中,其在0.25 μm CMOS 工艺条件下,芯片仿真结果表明,在500 mA~2 A的负载跳变条件下,与传统同步升压DC-DC转换器相比,芯片的响应恢复时间减小了45%,输出电压的下降和过冲值减少了35%。     

一种快速瞬态响应Buck变换器设计

提出了一种基于锁相环锁频锁相ACOT控制模式的Buck变换器。该变换器具有快速瞬态响应的特点。分析发现,在负载阶跃时,传统ACOT控制模式Buck变换器受到最小关断时间和锁相环速度的限制,不能完全发挥其瞬态响应快的优势。设计了一种根据设定的开关频率可自适应调节环路参数的Buck变换器,它在较宽的开关频率下具有快速的瞬态响应特性。采用0.18 μm BCD工艺对提出的Buck变换器进行仿真验证。结果表明,负载电流从1 A跳变到5 A时,输出电压下冲恢复时间减小为1.68 μs。     

测量开关电源闭环反馈响应

开关电源依靠反馈控制环路来保证在不同的负载情况下得到所需的电压和电流。反馈控制环路的设计影响到许多因素,包括电压调整、稳定性和瞬态响应。 当某个反馈控制环路在某个频率的环路增益为单位增益或更高且总的     

适用于高频开关芯片的快速瞬态响应LDO设计

设计了一种片外大电容快速瞬态响应低压差线性稳压器。该LDO电路基于跨导线性结构设计,在输出级引入推挽结构,有效地减小过冲的幅值和恢复时间,提高了LDO的瞬态响应速度;利用浮动缓冲器驱动功率管,有效地提高了LDO的电流效率;采用动态零点补偿技术,保证了LDO在全负载范围内的环路稳定性。该LDO电路基于0.35μm BCD工艺设计与仿真验证。结果表明,在1.2 V~3 V输入电压范围,LDO的输出电压为1 V,静态电流约为50μA,可提供0~300 mA的负载。在上升下降沿为500 ns、幅度为300 mA、轻载持续时间为50μs的负载瞬态跳变下,过冲和下冲均小于20 mV。电路满足高频负载跳变的应用需求。     

基于最优负载瞬态特性的单相全桥逆变器解耦设计

针对单相全桥工频逆变器设计过程欠缺规范的问题,该文提出了一种以动态设计指标为条件解耦设计主电路滤波参数和控制器参数的公式化分步设计法.以阻性负载跃变量为条件,分析了单相全桥工频逆变器在两种极端情况下的最优负载瞬态响应过程,推导了最优负载瞬态特性关于滤波参数的数学表达式,并给出了表达式适用范围-输出电压跌落量低于10%,且结合逆变器的动态设计指标提出了一种滤波器参数设计方法,再以滑模控制为例,结合动态设计指标给出了一种滑模控制器设计方法.仿真实验结果验证了最优负载瞬态响应过程的存在性,最优负载瞬态特性表达式的正确性和有效性,也验证了解耦设计法的正确性和有效性.该解耦设计法具有良好的理论价值和工程价值.     

基于电流环路控制方法的快速响应LDO

LDO电路的瞬态响应能力是评价LDO性能的一个重要指标。本文借鉴电荷泵式锁相环的环路控制方法,提出了一种基于电流控制环路的LDO结构,将典型LDO电路中的电压比较改为电流比较,利用跨导放大器和环路滤波器产生功率管的控制栅压,使得环路具有优化的阻尼因子ζ和固有频率ωn,有效提高了LDO环路的瞬态响应能力,并且输出电压可以低至1V以下,且不受基准电压的限制。基于0.13μm CMOS工艺的实现结果表明,在使用1μF去耦电容,LDO输出1.0V的情况下,负载100μA→100mA瞬态变化时,输出超调5.11mV,稳定输出的压降4.25mV,稳定时间8.2μs,而负载100mA→100μA时,输出超调6.21mV,稳定输出的压降4.25mV,稳定时间23.3μs。结果表明,该电路各项性能指标均有明显的提高,FOM指数达到0.0097。     

应用于前端读出电路的片上LDO设计

为满足辐射探测器前端读出电路对模拟电路稳压器片上集成和快速瞬态时间响应的需求,设计了一种基于0.18μm CMOS工艺的全片上集成LDO。采用大摆幅高增益放大器驱动输出功率管,增大了功率管栅极调节电压摆幅,减小了功率管尺寸和LDO压差电压。该放大器同时增大了LDO的环路增益和对功率管栅极的充放电电流,从而改善了瞬态响应性能。为了不牺牲环路增益带宽和芯片面积,并且保证LDO在整个负载电流区间内保持稳定,提出了一种负载电流分区频率补偿方法。仿真结果表明,在负载电容为200 nF,负载电流范围为0～200 mA时,设计的LDO相位裕度均大于53^o。在相同功率管尺寸情况下,采用大摆幅高增益放大器可以将LDO最大输出电流能力提高到两倍以上。当负载电流从10 mA跳变到200 mA时,LDO输出电压恢复时间小于6.5μs。设计的LDO电路面积为120μm×264μm,满载时电源效率为97.76%,最小压差电压为50 mV。     

星用基于UC1845多路输出双管反激开关电源设计

为了解决航天器DC/DC变换器高压输入多路输出时,开关管电压应力以及多路输出稳定度问题,设计了一种基于UC1845的多路输出双管反激开关电源。主电路采用双管反激式变换器,使主开关管上的电压应力仅为输入电压Vin,满足航天器高可靠性的应用需求;同时电路采用磁隔离反馈稳压控制,通过一个反馈控制量实现多路输出,输出端配合应用低压差三端稳压器,各路输出负载稳定度优于±1%。控制电路采用电流型控制器UC1845,其具有电压调整率高、负载调整率高和瞬态响应快等优点。实验结果表明,该电源安全可靠、稳定性好、纹波小、效率高,达到了设计要求。     

一种三环结构高效率的数字LDO电路

设计了一种采用0.18μm互补金属氧化物半导体(CMOS)工艺制作的三环结构无片外电容数字低压差线性稳压器(LDO)电路,主要在控制方式进行创新,针对不同的输出电压范围采取相应的环路进行调整.电路的功率MOS管阵列按MOS管尺寸,分为大(L)、中(M)、小(S)3组,设计的控制方式使环路可根据负载变化迅速切换,使得电路具有快速的瞬态响应,较强的带负载能力,较低的输出电压纹波和功耗,转换效率最高可达88.9%.在1.8 V输入电压下的后仿真结果表明,负载电流在2～60 mA之间突变时,电路的下冲电压为95 mV,过冲电压为80 mV,恢复时间小于1.7μs,稳态下的输出电压纹波小于2.0 mV,总体静态电流约为43μA.该数字LDO的输入电压范围为1～1.8V,输出电压范围为0.8～1.6 V,内部集成10 pF电容,品质因素FOM仅为0.009 pF.     

A high-performance ZVS full-bridge DC-DC 0-50-V/0-10-A power supplywith phase-shift control

This paper presents a high-performance DC-DC switching mode power supply designed to deliver a regulated 0-50 V/0-10 A output. The proposed power supply is based on a modified version of the zero-voltage switching (ZVS) full-bridge (FB) phase-shift DC-DC converter, which incorporates commutation auxiliary inductors to provide ZVS for the entire load range as well as a commutation aid circuit to clamp the output diode voltage. The control strategy is based on two control loops operating in cascade mode. The inner loop maintains a regulated output current, whereas the external voltage loop regulates the output voltage, independently of load and input-voltage changes. In order to obtain a high-reliability converter, the control circuit has been implemented using just two integrated circuits (ICs). The phase-shift regulator UC3875 IC generates the gate drive signal to the MOSFET's. The control loop regulators are implemented using the TL074 IC. A theoretical analysis was conducted, and experimental results were obtained for a 0-50 V/0-10 A power supply operating at 100 kHz     

A voltage mode buck DC–DC converter with automatic PWM/PSM mode switching by detecting the transient inductor current

This paper presents a voltage mode buck DC–DC converter that integrates pulse-width modulation (PWM) and pulse-skipping modulation (PSM) to achieve high efficiency under heavy and light load conditions, respectively. Automatic mode-switching is implemented simply by detecting the voltage drop of high-side power switch when it is on, which indicates the transient current flowing through the inductor. Unlike other methods based on average current sensing, the proposed auto-mode switching scheme is implemented based on voltage comparison and simple control logic circuit. In order to avoid unstable mode switching near the load condition boundary, the mode switching threshold voltage is set differently in PWM and PSM mode. Besides, a 16-cycle counter is also used to ensure correct detection of the change in the load condition and fast response of the converter. In addition, a dual-path error amplifier with clamp circuit is also adopted to realize loop compensation and ensure 100 % duty cycle operation. Fabricated in a 0.18-μm standard CMOS technology, the DC–DC converter is able to operate under supply voltage from 2.8 to 5.5 V with 3-MHz clock frequency. Measurement results show that the converter achieves a peak efficiency of 93 %, and an output voltage ripple of less than 40 mV, while the chip area is 1.02 mm².     

一种全数字控制两级级联大功率开关电源

设计了一种基于数字信号处理(DSP)的全数字控制两级级联大功率开关电源。在电路结构方面,采用了降压型和全桥式的变换器结构,其中,降压电路的占空比可随输出电压而调节,全桥电路能实现输入级与输出级的全隔离。在电路控制方面,采用数字比例-积分-微分(PID)控制技术,提升了系统的闭环控制速度和精度。该功率开关电源基于DSP的控制方法,构建了电源的控制系统。仿真及测试结果表明,基于DSP设计的开关电源具有稳定的性能和较高的效率,转换效率可达92%。     

An SC Voltage Doubler with Pseudo-Continuous Output Regulation Using a Three-Stage Switchable Opamp

This paper presents a switched-capacitor voltage doubler using pseudo-continuous control (PCC). The proposed PCC does not require extra power transistor to continuously regulate the output of the doubler, thereby saving chip area. The PCC also allows the doubler to operate at lower switching frequencies without sacrificing transient response. The light-load efficiency of the regulated doubler can thus be enhanced by reducing the switching power loss. In addition, a three-stage switchable opamp with time-multiplexed enhanced active-feedback frequency compensation is developed to implement the controller. The proposed implementation enhances the speed of the loop response and then improves the load transient response of the regulated doubler. The SC voltage doubler with the proposed PCC controller has been fabricated in a 0.6-mum CMOS process. The regulated doubler achieves >87% power efficiency even for the load current of 5 mA. By operating the doubler at switching frequency of 200 kHz and using a output capacitor of 2.2 muF, a maximum output ripple of 20mV is maintained for the load current changing from 50 mA to 150 mA. The output transient recovery time of the regulated doubler is ~25 mus with load-current step changes of 100 mA/1 mus     

CFAVC scheme for high frequency series resonant inverter-fed domestic induction heating system

This article presents the investigations on the constant frequency asymmetric voltage cancellation control in the AC–AC resonant converter-fed domestic induction heating system. Conventional fixed frequency control techniques used in the high frequency converters lead to non-zero voltage switching operation and reduced output power. The proposed control technique produces higher output power than the conventional fixed-frequency control strategies. In this control technique, zero-voltage-switching operation is maintained during different duty cycle operation for reduction in the switching losses. Complete analysis of the induction heating power supply system with asymmetric voltage cancellation control is discussed in this article. Simulation and experimental study on constant frequency asymmetric voltage cancellation (CFAVC)-controlled full bridge series resonant inverter is performed. Time domain simulation results for the open and closed loop of the system are obtained using MATLAB simulation tool. The simulation results prove the control of voltage and power in a wide range. PID controller-based closed loop control system achieves the voltage regulation of the proposed system for the step change in load. Hardware implementation of the system under CFAVC control is done using the embedded controller. The simulation and experimental results validate the performance of the CFAVC control technique for series resonant-based induction cooking system.     

一种适用于低ESR应用的高精度RBCOT环路

提出了一种适用于低ESR电容、具有快速瞬态响应和高输出精度的纹波控制COT(RBCOT)实现电路,并利用改进的等效三端开关模型,对包含分压网络的控制环路进行了精确的小信号建模。该环路在保持快速瞬态响应能力的同时,利用SW点的1阶滤波信号来产生虚拟电感电流纹波,避免了次谐波振荡现象。通过谷值采样电路,对滤波信号的谷值进行采样。采样电路在每个开关周期执行刷新操作,并在上电和瞬态变化阶段进行加速充电。纹波叠加电路将增强纹波和谷值采样信号精确地叠加到反馈电压端,保证电路输出精度较高。采用0.35μm 18 V BCD工艺,对纹波控制COT控制环路进行仿真。结果表明,在4.5~18 V输入电压范围内,输出电压的失调在1 mV范围以内,控制环路可以对瞬态变化进行快速调整。     

一种具有快速瞬态响应、小交调影响和纹波的基于次级纹波控制的单电感多输出电路

提出了一种主回路采用峰值电流型控制、次回路采用纹波控制的新型单电感多输出降压型开关电源的设计。这种设计,使单电感多输出的控制回路变得简单,同时也使瞬态响应速度变快,交调影响和纹波变小。其开关频率为2 MHz,两路输出分别为1.8 V和1.2 V,两路负载范围为0～200 mA,实现了全负载可以正常工作。在考虑了各种寄生参数的后仿真条件下,一路负载为200 mA,一路负载从50 mA变化到200 mA,瞬态响应速度小于3μs,交调影响小于0.05 mV/mA,纹波小于30 mV,峰值效率可以达到91%。该芯片已经在CHART 0.18-μm CMOS工艺上设计实现,正在流片验证。     

Nonlinear and vector closed-loop control methods for flying-capacitor power converters

In this paper, the design and implementation of two different, nonlinear and vector, closed-loop control methods for flying-capacitor power converters are proposed and evaluated. Specific focus has been given to the decoupling problem, the influence of the balancing compensator on the output voltage reference tracking controller. In the first method, the coupling between the internal voltage balancing dynamics and the external load dynamics is solved in the pulse-width modulator by means of vector modulation. In the second method, input–output decoupling is achieved by feedback linearization to resolve the nonlinearity caused by switching the flying-capacitor voltage state. For both methods, classical linear control theory is applied in the design of a feedback control law. The theoretic evaluation is supported by simulation and experimental results.     

Dead-zone digital controllers for improved dynamic response of low harmonic rectifiers

This paper introduces a simple digital control method that enables fast regulation of the output voltage in low harmonic rectifiers with power factor correction (PFC). The method is based on the use of an insensitive region, i.e., "dead-zone," in analog-to-digital conversion, for elimination of the output capacitor voltage ripple in the feedback loop. The dead-zone can either be fixed and larger than the maximum ripple magnitude, or it can be dynamically adjusted in accordance with the output load. Simple implementations of these two dead-zone controllers are shown on an experimental completely digitally controlled 250-W boost PFC operating at 200-kHz switching frequency. The experimental results show that this control method results in low current harmonics and improved load transient responses, which are significantly faster than in low-harmonic rectifiers with conventional low-bandwidth voltage-loop controllers.     

A dual-mode fast-transient average-current-mode buck converter without slope-compensation

A dual-mode fast-transient average-current-mode buck converter without slope-compensation is proposed in this paper. The benefits of the average-current-mode are fast-transient response, simple compensation design, and no requirement for slope-compensation, furthermore, that minimizes some power management problems, such as EMI, size, design complexity, and cost. Average-current-mode control employs two loop control methods, an inner loop for current and an outer one for voltage. The proposed buck converter using the current-sensing and average-current-mode control techniques can be stable even if the duty cycle is greater than 50%. Also, adaptively switch between pulse-width modulation (PWM) and pulse-frequency modulation (PFM) is operated with high conversion efficiency. Under light load condition, the proposed buck converter enters PFM mode to decrease the output ripple. Even more, switching PWM mode realizes a smooth transition under heavy load condition. Therefore, PFM is used to improve the efficiency at light load. Dual-mode buck converter has high conversion efficiency over a wide load conditions. The proposed buck converter has been fabricated with TSMC 0.35 μm CMOS 2P4M processes, the total chip area is 1.45×1.11 mm². Maximum output current is 450 mA at the output voltage 1.8 V. When the supply voltage is 3.6 V, the output voltage can be 0.8-2.8 V. Maximum transient response is less than 10 μs. Finally, the theoretical analysis is verified to be correct by simulations and experiments.