一款异步256kB SRAM的设计

在集成电路设计制造水平不断提高的今天,SRAM存储器不断朝着大容量、高速度、低功耗的方向发展。文章提出了一款异步256kB(256k×1)SRAM的设计,该存储器采用了六管CMOS存储单元、锁存器型灵敏放大器、ATD电路,采用0.5μm体硅CMOS工艺,数据存取时间为12ns。     

一种阵列布局优化的256 kb SRAM

介绍了一种阵列布局优化的256 kb(8 k×32位)低功耗SRAM。通过采用分级位线和局部灵敏放大器结构,减少位线上的负载电容;通过电压产生电路,获得写操作所需的参考电压,降低写操作时的位线电压摆动幅度,有效地减少了SRAM读写操作时的动态功耗。与传统结构的SRAM相比,该256 kb SRAM的写功耗可减少37.70 mW。     

SRAM灵敏放大器的设计改进及其Hspice仿真分析

静态随机存取存储器（SRAM）由于其自身的低功耗和高速的优势而成为半导体存储器中不可或缺的重要产品。提高和改善静态存储器的性能依然是集成电路设计领域的重要课题。从降低静态存储器功耗的角度出发，重点研究了静态存储器的关键模块——灵敏放大器的工作机理和结构，设计了一种改进型的锁存型灵敏放大器，Hspice的仿真表明，该放大器的功耗大大低于传统的静态存储器的灵敏放大器模块的功耗。     

基于补偿电路的SRAM读操作跟踪电路设计

在传统静态随机存储器（SRAM）读操作跟踪电路中,生产工艺和温度的偏差会直接影响到对SRAM中存储数据的正确读取。因此,在本文中,我们采用工艺拐点补偿和温度补偿的方法,设计出了新型SRAM读操作跟踪电路。所设计跟踪电路,通过在不同工艺拐点和不同温度的情况下,对时序追踪字线DBL补偿不同大小的电流,从而减小灵敏放大器输入位线电压差对工艺拐点和温度的敏感度。有效减小了工艺拐点和温度对于SRAM读操作的影响,提高了SRAM的良率。基于SMIC 40nm CMOS工艺,对上述读操作跟踪电路进行了仿真,并且分别对补偿前后进行了10000次蒙特卡罗仿真与比较,仿真结果验证了所设计电路的可靠性和有效性。     

一种新型灵敏放大器的设计

文章分析了基本锁存器型灵敏放大器结构,总结了其优缺点,在此基础上设计出一种高速低功耗的SRAM灵敏放大器,在输入差分信号建立之后,读出放大时间在最坏情况下需0.5ns。利用两级敏感放大器的层次式结构,一方面使第一级放大的信号成为真正的数字信号,另一方面增加了电路的驱动能力。     

用于非制冷红外探测器片上存储器的低延迟灵敏放大器设计北大核心CSCD

针对非制冷红外探测器片上存储器的高速数据读出,设计了一种用于非制冷红外探测器片上存储器的低延迟灵敏放大器。随着非制冷红外探测器像素阵列的不断加大,对非制冷红外探测器片上存储器的要求也更高,需要一个更高速的存储器进行红外探测器内部数据存储。通过降低灵敏放大器延迟时间是提高数据传输速度的一种可靠方法。本文对传统交叉耦合结构灵敏放大器进行改进,与传统交叉耦合结构灵敏放大器相比,增加了完全互补型的第二级交叉放大电路,并采用NMOS组成的中间阶段进行两级运放的耦合。改进后的新型灵敏放大器能快速有效地放大位线上电压差,同时改善灵敏度低的问题。本论文设计的灵敏放大器采用TSMC 65 nm工艺,在工作电压为5 V、位线电压差为100 mV条件下,仿真结果表明:数据读出延迟仅为25.19 ps,与交叉耦合式灵敏放大器相比,读出延迟降低了37.07%。同时,在全工艺角仿真条件下,环境温度为-45—125℃,新型灵敏放大器延迟仿真最大值仅为39 ps,最小值为17.1 ps。     

SRAM存储器动态参数测试向量分析

半导体存储器一般由存储体、地址译码驱动器、读/写放大器和控制电路组成,是一种能存储大量信息的器件,它是由许多存储单元组成的。半导体存储器的测试有功能测试、直流参数测试、交流参数测试,而功能测试和交流参数测试对存储器来说是至关重要的。SRAM(静态随机存储器)的功能测试是通过算法图形发生器产生不同的测试图形,对被测器件各个不同存储单位进行读写操作,以检查其功能。主要讲述了SRAM交流参数测试原理及其测试关键技术,介绍了SRAM交流参数测试的故障模型。通过研究SRAM交流参数测试图形向量,给出了SRAM交流参数测试图形向量的优化方法。     

一种4-Mb高速低功耗CMOS SRAM的设计

高性能的系统芯片对数据存取速度有了更严格的要求,同时低功耗设计已成为VLSI的研究热点和挑战.本文设计了一款4-Mb(512K×8bit)的高速、低功耗静态存储器(SRAM).它采用0.25μm CMOS标准工艺和传统的六管单元.文章分析了影响存储器速度和功耗的原因,重点讨论了存储器的总体结构、灵敏放大器及位线电路.通过系统优化,达到15ns的存取时间.     

一种新型的SOI灵敏放大器

本文利用"灵巧的体接触(Smart-Body-Contact)"技术设计出一种新型的SOI灵敏放大器.采用Hspice软件对体硅的和新型的交叉耦合灵敏放大器进行模拟和比较,发现新型的交叉耦合灵敏放大器比体硅的交叉耦合灵敏放大器延迟时间缩短30%,最小电压分辨可达0.05V.最后,我们成功地将该电路应用于CMOS/SOI 64Kb SRAM电路,电路存取时间仅40ns.     

CMOS/SOI 64Kb静态随机存储器

对一种CMOS/SOI 64Kb静态随机存储器进行了研究,其电路采用8K×8的并行结构体系．为了提高电路的速度,采用地址转换监控(Address-Translate-Detector,ATD)、两级字线(Double-Word-Line,DWL)和新型的两级灵敏放大等技术,电路存取时间仅40ns;同时,重点研究了SOI静电泄放(Electrostatic-Discharge,ESD)保护电路和一种改进的灵敏放大器,设计出一套全新ESD电路,其抗静电能力高达4200—4500V．SOI 64Kb CMOS静态存储器采用1.2μm SOI CMOS抗辐照工艺技术,芯片尺寸为7.8mm×7.24mm．     

500-Mb/s nonprecharged data bus for high-speed DRAM's

A nonprecharged data-bus scheme to enhance the intrinsic read data rate of DRAM cores is proposed. Eliminating the precharge cycle of the DRAM data bus can reduce the unit bit time. A differential partial response detection data-bus amplifier is also employed to detect signals on the nonprecharged data bus that are degraded by large intersymbol interference. To enhance the read operation further, column selections are overlapped by interleaved column decoders. To increase the operating margin of the nonprecharged data-bus read, a skew-controlled column-selection pulse generator was developed. An isolated sense-amplifier scheme increases the write data rate of the DRAM core. To verify these schemes, a 4-Mb DRAM was fabricated via 0.24-μm DRAM technology. These schemes realized a 500-Mb/s per data-bus read operation and a 100-Mb/s per data-bus write operation without an area penalty     

A bitline leakage compensation scheme for low-voltage SRAMs

A bitline leakage current of an SRAM, induced by leakage current of the transmission transistors in the cells that are associated with the bitline, increases as the threshold voltage (V_TH) of the transistors is reduced for high performance at low power-supply voltage (V_DD). The increased bitline leakage causes slow or incorrect read/write operation of an SRAM because the leakage current acts as noise current for a sense amplifier. In this paper, the problem has been solved from a circuitry point of view, and the scheme which detects the bitline leakage current in a precharge cycle and compensates for it during a read/write cycle is proposed. Employing this scheme, the SRAM with 360-μA bitline leakage current can perform a read/write operation at the same speed as one that has no bitline leakage current. This enables a 0.1-V reduction in V_TH, and keeps the V_TH and delay scalability of a high-performance SRAM in technology progress. An experimental 8-Kb SRAM with 256 rows is fabricated in a 0.25-μm CMOS technology, which demonstrates the effectiveness of the scheme     

适用于射频识别标签的64-kbit嵌入式阻变存储器

设计并实现了一颗适用于射频识别(RFID)标签的低功耗嵌入式64-kbit阻变存储器芯片.提出了新型的带尖峰电流控制功能的高压稳压电路,在提供稳定编程电压的同时降低了芯片电源上的瞬态大电流,改善了存储器电路的可靠性;设计了适用于2T2R(2 Transistors and 2 Resistive cells)单元的敏感...     

A 1.6-Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control

An 8 M /spl times/ 32 GDDR (graphic DDR) SDRAM operating up to 800-MHz clock (CLK) frequency is described. The GDDR SDRAM demands an effective control of CAS latency due to the large and wide number of CAS latencies at the CLK frequency. A wave-pipelined CAS latency control circuit is proposed to provide stable operation for the large and wide number of CAS latencies. The increase of CAS latency also causes a degradation of data bus efficiency at high-speed operation due to the large gap between input data (DINs) and output data (DOUTs) at the operation of write followed by read. A gapless write to read scheme improves the data bus efficiency by separating write data-path from read data-path for different banks accesses. Partial array activation commands can reduce the peak current, preventing the reduction of the data retention time of DRAM cells at high-speed operation. The GDDR SDRAM operates successfully at the CLK frequency of 800 MHz at 2.1 V and 700 MHz at 1.8 V, respectively. The power consumption is measured to be /spl sim/2 W at 1.9 V.     

一种高性能的异步FIFO结构

针对现有FIFO设计方法的不足,本文提出一种新的异步FIFO结构——WG-FIFO,采用加权Gray码进行指针编码,采用实时状态检测器控制写/读操作.模拟结果表明,在FIFO深度为4~16的情况下,该结构与已有的FIFO结构相比在性能、面积开销以及写/读操作效率等方面都获得了明显的改善.特别地,当FIFO的深度为8、宽度为32时,相比B-FIFO,WG-FIFO的最高时钟频率提高31.6%,单元面积减少17.1%,且写/读效率最大能提高47%.     

A 6-ns 1-Mb CMOS SRAM with latched sense amplifier

A 1-Mb (256 K×4) CMOS SRAM with 6-ns access time is described. The SRAM, having a cell size of 3.8 μm×7.2 μm and a die size of 6.09 mm×12.94 mm, is fabricated by using 0.5-μm triple-polysilicon and double-metal process technology. The fast access time and low power dissipation of 52 mA at 100-MHz operation are achieved by using a new NMOS source-controlled latched sense amplifier and a data-output prereset circuit. In addition, an equalizing technique at the end of the write operation is used to avoid lengthening of access time in a read cycle following a write cycle     

A design for high noise rejection in a pseudodifferentialpreamplifier for hard disk drives

A study of supply and system noise rejection for a pseudodifferential amplifier is presented in this paper. This pseudodifferential amplifier is aimed at high data-rate disk drive signal sensing and preamplification applications. This high rejection was achieved by improving the rejection of the pseudodifferential amplifier and also by carefully designing the interconnect flex circuit where the preamplifier is mounted. The measured rejection to power supply, ground and system noise is above 50 dB over a 300 MHz bandwidth. This is significant for a pseudodifferential amplification system. The gain of the preamplifier is 47 dB and write mode to read mode switching time is 210 ns. This preamplifier currently supports disk drive data rates over 270 Mb/s     

Novel low-power and stable SRAM cells for sub-threshold operation at 45 nm

In scaled technologies with lower supply voltage, conventional Static Random Access Memory (SRAM) cell suffers from unsuccessful read & write operation due to high off state current in sub-threshold region at nanometre technologies. This work proposes new functional low-power designs of SRAM cells with 7, 8, 9 and 12 transistors which operate at only 0.4V power supply in sub-threshold operation at 45 nm technology. Stability analysis is carried out using static noise margins as well as N-curve cell stability metrics. For performance measurement, read/write access time and leakage power consumption in hold mode are analysed. The comparison with published designs shows that two new proposed designs namely M8T, MPT8T have 30% less leakage power consumption along with 2× read stability, 2× write ability, more than 60% faster read & write operation.     

A new write/erase method to improve the read disturbcharacteristics based on the decay phenomena of stress leakage currentfor flash memories

This paper describes a new write/erase method for flash memory to improve the read disturb characteristics by means of drastically reducing the stress leakage current in the tunnel oxide. This new write/erase operation method is based on the newly discovered three decay characteristics of the stress leakage current. The features of the proposed write/erase method are as follows: 1) the polarity of the additional pulse after applying write/erase pulse is the same as that of the control gate voltage in the read operation; 2) the voltage of the additional pulse is higher than that of a control gate in a read operation, and lower than that of a control gate in a write operation; and 3) an additional pulse is applied to the control gate just after a completion of the write/erase operation. With the proposed write/erase method, the degradation of the read disturb life time after 10⁶ write/erase cycles can be drastically reduced by 50% in comparison with the conventional bipolarity write/erase method used for NAND type flash memory. Furthermore, the degradation can he drastically reduced by 90% in comparison with the conventional unipolarity write/erase method fur NOR-, AND-, and DINOR-type flash memory. This proposed write/erase operation method has superior potential for applications to 256 Mb flash memories and beyond     

Shared word line DRAM cell

A novel memory cell which has a 2-to-1 cell packaging density advantage relative to a conventional one-device (1D) dynamic RAM cell is described. In the shared word line (SWL) DRAM cell, a pair of cells is connected to the same bit sense line and word line. Unique read and write operations are accomplished by controlling the plate of the storage capacitor. The arrangement of cell pairs also provides a sense amplifier pitch of about six times the average feature size; this greatly relaxes the bit line pitch limitation on sense amplifier layout. The cell layout is fully self-aligned using a process very similar and not significantly more complex than conventional double-polysilicon processes. The cell requires neither contact holes nor metal lines. While the access time of the SWL cell is similar to a 1D cell, the cycle time is somewhat longer due to a more complex write operation.