一种二阶曲率补偿的高精度带隙基准电压源

提出了一种输出电压可调的带隙基准电路．通过对双极晶体管基极-发射极电压的二阶温度补偿,大大改善了带隙基准的温度特性,并增加嵌套密勒补偿,进一步提高了系统的稳定性．基于0.6μm CMOS工艺,利用Hspice进行了仿真验证,结果表明,在-40～120℃温度范围内,0.8V基准电压的温度系数为6.1×10^-6／℃,低频时电源抑制比为-82dB,正常工作时静态工作电流小于6.5μA．     

一种结构简单的曲率补偿CMOS带隙基准源

提出了一种结构简单新颖的高性能曲率补偿带隙电压基准源．电路设计中没有采用典型结构中的差分放大器,而是采用负反馈技术实现电压箝位,简化了电路结构; 输出部分采用调节型共源共栅结构,保证了高的电源抑制比．整个电路采用SMIC 0.18μm标准CMOS工艺实现,并用HSPICE进行仿真,结果表明所设计的电路在-45℃～125℃范围内的温度系数为12.9×10^-6／℃,频率为10Hz时的电源抑制比为67.2dB．该结构可应用于高速模数转换器的设计中．     

一种CMOS高阶曲率补偿的带隙基准源电路的设计

为解决传统CMOS带隙基准电压源的温度系数较高的问题,采用高阶曲率补偿方法,提出了一种新型的带隙基准电压源,这种基准电压源的结构简单同时具有良好耗能性能,并且基准电压的温度系数得到一定的优化.利用NMOS管工作在亚阈值区域时漏电流和栅源电压的非线性特性,通过引入与基准电压温度系数成相反趋势的高阶补偿电流,降低基准电压的温度系数,以较少的硬件消耗为代价大幅提高了其温度特性,最后推导出补偿后的基准电压的计算公式.基于0.18μm BCD工艺进行仿真,结果表明:在-40℃~150℃温度范围内,基准电压的温度系数为6.94×10~(-6);电源电压VDD在2.5~5.0 V范围内,线性调整率为0.033%,电路在5 V电源电压为下工作电流为7.36μA;在典型工艺下(TT),电源抑制比(PSRR)为77.4 dB.基准电压的温度特性的理论分析结果与仿真结果吻合较好,通过高阶补偿后,带隙基准电压源表现出优良的性能,满足了带隙基准源的低功耗和低温漂的设计要求.     

一种高电源抑制比带隙基准电压源的设计

采用共源共栅运算放大器作为驱动,设计了一种高电源抑制比和低温度系数的带隙基准电压源电路,并在TSMC 0.18μm CMOS工艺下,采用HSPICE进行了仿真.仿真结果表明:在-25～115℃温度范围内电路的温漂系数为9.69×10-6/℃,电源抑制比达到-100 dB,电源电压在2.5～4.5 V之间时输出电压Vref的摆动为0.2 mV,是一种有效的基准电压实现方法.     

CMOS带隙基准电压源电路的模拟

利用CSMC0．6μmCMOS标准工艺及OrCAD模拟电路设计软件环境,设计了2种具有曲率补偿的带隙基准电压源电路,并用Hspice对电路的温漂、电源抑制比、电源电压稳定性及电路功耗进行了仿真。仿真结果表明,第1种在-20℃～130℃温度范围内,温度系数为29．97×10^-6／℃;第2种在-20℃～130℃温度范围内,温度系数为12．73×10^-6／℃。     

一种用电流基准核作温度互补性补偿的基准电压源

为克服传统带隙基准源在温度性能上的缺陷,设计了一种低温度系数的带隙基准电路。该电路在传统电流模基准结构的基础上,引入一个工作在亚阈值区电流基准核产生的电流来达到高阶补偿的目的。在一阶补偿的基础上,补偿电流的进一步补偿,大大降低了基准输出的温度系数。电路设计采用0.18μm的CMOS工艺,利用Cadence软件的Spectre仿真工具对电路进行仿真,仿真结果表明,在2.7V电源电压下,基准输出电压为1.265V,温度在-40～125℃变化时,基准输出电压仅变化0.2mV,相比一阶补偿的变化（约为2.5mV）,精度提升了10多倍;电源电压在1.8～3.5V变化时,基准输出电压变化4.5mV;在出色的温度性能下有良好的抗干忧性,满足了高性能基准源的要求。     

高性能分段温度曲率补偿基准电压源设计

针对带隙基准电压源温漂高、电源抑制比(PSRR)低的问题,提出一种新颖的分段曲率补偿技术.该电路将基准源工作的全温度范围划分为3个区间,对各段温度区间进行不同的温度补偿,同时引入电流环负反馈结构,提高电路在低频时的电源抑制比,实现在-40～150℃内,温度系数为1.24×10-6,在DC时电源抑制比为-137dB.该电路采用TSMC0.6μmBCD工艺设计实现,芯片面积为0.5mm2,关断电流小于0.1μA,工作静态功耗为125μW.投片测试结果验证了电路设计的正确性,当电源电压为2.5～6.0V时,该基准源输出电压摆幅仅为0.220mV.     

一种新颖自偏置带隙基准电压源的设计

基于0.6μm BCD工艺参数,设计了一种新颖的低温漂、低功耗、高电源抑制比的自偏置带隙基准电压源.电路仿真结果表明:其工作电源电压低至1.7V,输出基准电压为1.24 V,温度系数仅6.68×10-6V/℃,电流消耗22 μA,电源抑制比高达82 dB.该电压源可广泛应用于模/数、数/模转换电路和电源管理芯片中.     

带有修调的分段曲率补偿带隙基准电路

为得到高精度低温度系数、高电源抑制比的基准电压,同时为了降低工艺中非理想性因素的影响,设计了一种新的带有修调的分段曲率补偿基准电路. 通过利用电阻分压和工作在亚阈值区域的MOSFET的电学特性,产生正温度系数和负温度系数的电流,在高温段和低温段分别对带隙基准电压进行曲率补偿,提出了一种新的快速优化基准电压温度系数的芯片级修调方法,包含温度系数修调和电压幅值修调,可以快速获得最低温度系数对应码值以提升工作效率.基于0.35 μm BCD工艺,流片验证了该修调方案的可行性.结果表明:在-40℃~125℃内,基准电压最低仿真温度系数为0.84×10^-6/℃,最低实测温度系数为5.33×10^-6/℃,随机抽样结果显示温度系数的平均值为7.47×10^-6/℃;采用基于计算斜率的修调方法,测试10块芯片的平均修调次数为3.5次,与使用逐次逼近的修调方法相比,效率提升59.8％;低温度系数的带隙基准电压有利于提升电池管理芯片对电池剩余电量估算的准确性,该带隙基准电路已成功应用于电池管理芯片内高精度模数转换器中.     

非线性补偿的低温漂低功耗CMOS带隙基准源的设计

设计了一种基于电流模式的具有非线性补偿的低温漂低功耗带隙基准电压源,在传统电路的基础上增加一个三极管和两个电阻达到对双极型晶体管的发射结电压VBE中与温度相关的非线性项的补偿。电路采用CSMC0.5μmDPTM CMOS工艺制造。该电路结构简单,在室温下的输出电压为1.217V,在?40℃～125℃的范围内温度系数为4.6ppm/,℃在2.6～4V之间的电源调整率为1.6mV/V。在3.3V的电源电压下整个电路的功耗仅为0.21mW。     

一种适用于移动芯片的低功耗低温漂LDO电路

针对移动设备低功耗的要求,基于GSMC 0.18μm CMOS集成电路工艺,设计了一种新型无片外电容低压差线性稳压电路．在传统结构的基础上,用经温度补偿的恒流源替代反馈电阻,并将此恒流源作为基准电压源电路及误差放大器偏置参考电流,降低了静态功耗,同时对输出电压实现了温度补偿且可调．结果表明,在2.85～4.00V工作电压范围内,空载时静态电流仅为5.486μA; 在-40~85℃工作温度范围内,输出电压温漂为9.772×10^-6/℃;电路版图面积仅为0.12mm×0.09mm．     

Curvature Compensated CMOS Bandgap Reference with Novel Process Variation Calibration Technique

A lowtemperature coefficient( TC) bandgap reference( BGR) with novel process variation calibration technique is proposed in this paper. This proposed calibration technique compensating both TC and output value of BGR achieves fine adjustment step towards the reference voltage,while keeping optimal TC by utilizing large resistance to help layout match. The high-order curvature compensation realized by poly and p-diffusion resistors is introduced into the design to guarantee the temperature characteristic. Implemented in 180 nm technology,the proposed BGR has been simulated to have a power supply rejection ratio( PSRR) of 91 dB@100 Hz. The calibration technique covers output voltage scope of 0. 49 V-0. 56 Vwith TC of 9. 45 × 10~(-6)/℃-9. 56 × 10~(-6)/℃ over the temperature range of-40 ℃-120 ℃. The designed BGR provides a reference voltage of 500 mV,with measured TC of 10. 1 × 10~(-6)/℃.     

Design of a low temperature coefficient bandgap reference with a wide temperature range

In order to meet the requirements of different applications and markets for the accuracy and reliability of IoT chips,a low temperature coefficient bandgap reference with a wide temperature range is proposed.On the basis of the traditional Banba bandgap reference structure,the circuit utilizes high-order temperature compensation technology and piecewise temperature compensation technology to improve the curvature of the output reference voltage.The temperature coefficient of the circuit is reduced.At the same time,the operating temperature range of the circuit is extended.The circuit performances are verified in the TSMC 180 nm CMOS process.Test results show that the temperature coefficient of the circuit is as low as 7.2×10^-6/℃ in the range of-40 ℃ to 160 ℃.The power supply rejection ratio at a low frequency is -48.52 dB.The static current under the 1.8 V power supply voltage is 68.38 μA,and the core area of the chip is 0.025 mm².     

High voltage detection circuit for power over the ethernet

A novel high voltage detection circuit with a high accuracy and low temperature coefficient for Power over the Ethernet (PoE) application is presented. The proposed detection circuit uses a bandgap comparator to detect the input voltage without an extra comparator and a voltage reference circuit, which reduces the chip area and detection time. In order to overcome the effect of the Ethernet resistor and avoid the circulating change of the detection circuit between the detection state and classification state, the proposed circuit uses a feedback circuit to realize the hysteresis function. The proposed detection circuit is implemented in 0.5μm65 V BCD process which occupies an active area of 590μm×310 μm. The measured results show that the temperature coefficient of the threshold voltage is 26.5×10^-6／℃ over the temperature range of -40℃ to 125℃. According to the measured results of 20 chips, the average value of the threshold voltage is 11.9V±0.25V, with a standard deviation of 0.138V.     

Low-offset high-PSRR bandgap voltage reference

Based on the problem that the accuracy of the bandgap affects the performance of the integrated circuit, a novel BGR (bandgap voltage reference) is proposed. It utilizes a feedback compensation network to enhance PSRR and reduce the offset voltage, which improves the system stability and precision. Cadence spectre simulation has been done by the SMIC 018μm 1.8V CMOS process for validation. The results show that the achieved temperature coefficient is 34.6×10^-6/℃ over -30℃ to 100℃ and that the PSRR is -63.5dB at a low frequency. The power assumption is only 1.5μW. The circuit is suitable for a low-voltage low-power energy harvesting system.     

A band-gap voltage reference for interface circuit of microsensor

A high performance CMOS band-gap voltage reference circuit that can be used in interface integrated circuit of microsensor and compatible with 0. 6 μm ( double poly) mix process is proposed in this paper. The circuit can be employed in the range of 1. 8 - 8 V and carry out the first-order PTAT ( proportional to absolute temperature) temperature compensation. Through using a two-stage op-amp with a NMOS input pair as a negative feedback op-amp,the PSRR ( power supply rejection ratio) of the entire circuit is increased,and the temperature coefficient of reference voltage is decreased. Results from HSPICE simulation show that the PSRR is - 72. 76 dB in the condition of low-frequency,the temperature coefficient is 2. 4 × 10 -6 in the temperature range from - 10 ℃ to 90 ℃ and the power dissipation is only 14 μW when the supply voltage is 1. 8 V.     

High precision voltage reference generator for 16-bit 100MS/s ADC

An output adjustable voltage reference generator for the 16-bit 100MS/s pipelined ADC is presented. An adjustable output voltage, fast-setting, high precision reference voltage buffer is designed by using current summing and floating current control techniques. In order to further improve the PSRR and reduce the output impedance, the push pull output and replica circuit structure is introduced. The prototype 16-bit 100MS/s ADC is fabricated by 0.18μm 1.8V 1P6M CMOS technology.Test results show that the voltage reference generator consumes an area of 1.3mm×2.0mm, and the power consumption is 23mW. The average temperature coefficient of the output voltage is 16×10^-6℃^-1 in the range of -55℃ to 125℃. The 16-bit 100MS/s ADC achieves the SNR of 76.3dBFS and SFDR of 89.2dBc, with 10.1MHz input at the full sampling speed, and it consumes the power of 300mW and occupies an area of 3.5mm×5.0mm.     

一种高精度低温漂带隙基准源的设计

该文参考了带隙基准电压源领域的现阶段技术,结合自偏置共源共栅电流镜以及适当的启动电路、补偿电路,设计了一种高精度、低温漂的多输出带隙基准电路。首先简述了传统带隙电压基准的基本原理,然后详细阐述了具体的各电路设计过程。该基准电压源可广泛应用于电源管理芯片等对能耗要求极高的芯片中。