深结短沟道MOS晶体管准二维阈值电压模型

提出了一个新的短沟道MOS晶体管表面势的准二维解析模型。不同于经典模型,该模型对沟道耗尽层横向剖分,由高斯定理导出沟道耗尽层电势的一维微分方程,方程考虑了漏、源的横向电场对沟道耗尽层厚度的影响。求解方程得到了耗尽层厚度与表面势的关系函数,由此得出了一个包含有沟道长度的阈值电压公式。通过MEDICI软件对多种不同参数的MOS晶体管进行了仿真,此模型计算结果与MEDICI仿真数据吻合较好,比电荷分享模型精度高。     

非均匀沟道DMOS器件阈值电压模型

提出了DMOS器件的二维电荷阈值电压模型。基于沟道区杂质的二维分布,求解泊松方 程,得到沟道区中耗尽电荷总量,给出DMOS二维阈值电压模型的解析式。该模型的解析解与实验 结果和数值解相吻合。并对DMOS的短沟效应和阈值电压与沟道表面扩散浓度、沟道结深和沟道 长度等参数的关系进行了深入分析,给出了短沟DMOS器件阈值电压的解析式。文中还给出了沟 道表面掺杂浓度在2.0×1016cm-3到10.0×1016cm-3范围内DMOS器件的阈值电压简明计算式。该 模型解决了习用的DMOS器件阈值电压模型解析值比实验结果大100％以上的问题。     

窄沟MOSFET的阀值电压

本文导出了窄沟MOS场效应晶体管阀值电压的简单闭式解析式。窄沟模型给出阀值电压与栅氧化层厚度、沟道掺杂浓度、背面栅偏压和沟道宽度的关系式。把理论计算的结果与实验结果进行了比较,二者非常接近。     

考虑二维量子力学效应的MOSFET解析电荷模型

在亚 5 0 nm的 MOSFET中 ,沿沟道方向上的量子力学效应对器件特性有很大的影响。基于 WKB理论 ,考虑MOSFET中该效应对垂直沟道方向上能级的影响 ,引入了其对于阈电压的修正。在此基础上 ,对沟道方向的子带作了抛物线近似 ,从而建立了一个考虑二维量子力学的电荷解析模型。根据该模型 ,得到二维量子力学修正和沟道长度以及其他工艺参数的关系。与数值模拟结果的比较表明 ,该解析模型的精度令人满意 ,并且得出以下结论 :二维量子力学效应使阈电压下降 ,并且在亚 5 0 nm的 MOSFET中 ,这个修正不可忽略。     

短沟Trench MOSFET阈值电压解析模型

传统MOS器件的阈值电压模型被广泛地用于分析Trench MOSFET的阈值电压,这种模型对于长沟道和均匀分布衬底的MOS器件来说很合适.但是对于Trench MOSFET器件来说却显现出越来越多的问题,这是因为Trench MOSFET的沟道方向是垂直的,其杂质分布也是非均匀的.本文基于二维电荷共享模型,给出了Trench MOSFET的一种新的阈值电压解析模型,该模型反映了器件的阈值电压随不同结构和工艺参数变化的规律,模型的结果和器件仿真软件Sivaco TCAD的仿真结果吻合较好.该模型较好地解决了以往所用的Trench MOSFET阈值电压模型计算不准确的问题.     

GaAs MESFET栅取向效应中背栅的作用

根据压电效应模型,本文详细研究了压电电荷对GaAs MESFET沟道与衬底界面耗尽层的影响。认为正压电电荷比负压电电荷所引起的阀值电压漂移大,较好解释了(100)衬底上沿[011]和[011]取向的GaAs MESFET阈值电压非对称反向漂移的现象。     

DMOS辐照正空间电荷阈值电压模型

提出了一种DMOS辐照正空间电荷闽值电压模型。基于沟道杂质的非均匀分布，借助镜像法，导出辐照正空间电荷与沟道电离杂质的二维场和二维互作用势；求解泊松方程，由此给出DMOS辐照正空间电荷阈值电压模型表示式。该模型的解析解与MEDICI仿真的数值解吻合。     

DMOS阈值电压二维模型

提出了DMOS器件的二维阈值电压模型,分析了耗尽层宽度的变化,并得到了模型的数学表达式.模型的解析解与实验结果和二维仿真器MEDICI的数值解相吻合.给出了沟道表面扩散浓度在2.0×1016～10.0×1016cm-3范围内DMOS器件的阈值电压简明计算式.该模型的提出解决了以往所用的DMOS阈值电压模型计算很不准确的问题.     

DMOS阈值电压二维模型

提出了DMOS器件的二维阈值电压模型 ,分析了耗尽层宽度的变化 ,并得到了模型的数学表达式 .模型的解析解与实验结果和二维仿真器MEDICI的数值解相吻合 .给出了沟道表面扩散浓度在 2e16～ 10 e 10 16cm-3 范围内DMOS器件的阈值电压简明计算式 .该模型的提出解决了以往所用的DMOS阈值电压模型计算很不准确的问题 .     

扩散杂质分布对V—MOS,D—MOS器件的直流特性的影响

为了研究杂质分布对器件性能的影响模仿双扩散MCS（D—MOS）和V—沟道MOS（V—MOS）晶体管的结构,改变的工艺系数选用沟道长度了沟道掺杂值的范围。用两探测扩展电阻的方法来量测杂质的分布。以VMOS和DMOS器件的电学特性的比较来推示横向DMOS杂质分布的特性。发现一般的方法不能模拟器件的输出电导。实际上沟道长度的计算是在沟道漏结周围,方程的一维解。当测量杂质分布数据时,引进新的沟道长度计算方法,在沟道长度为0.6～um时,器件的输出电导能确的模拟。     

短沟DMOS阈值电压模型

该文提出了短沟DMOS阈值电压模型。基于沟道区耗尽电荷的二维分布,计算沟道区中耗尽电荷总量,由此给出短沟DMOS阈值电压模型的计算式。该模型的解析解与二维仿真器MEDICI的数值解吻合。分析表明,DMOS沟道长度小于0.80m,就应考虑短沟效应。     

A threshold voltage model for short-channel MOSFETs taking into account the varying depth of channel depletion layers around the source and drain

In this paper, an analytical model for threshold voltage of short-channel MOSFETs is presented. For such devices, the depletion regions due to source/drain junctions occupy a large portion of the channel, and hence are very important for accurate modeling. The proposed threshold voltage model is based on a realistic physically-based model for the depletion layer depth along the channel that takes into account its variation due to the source and drain junctions. With this, the unrealistic assumption of a constant depletion layer depth has been removed, resulting in an accurate prediction of the threshold voltage. The proposed model can predict the drain induced barrier lowering (DIBL) effect and hence, the threshold voltage roll-off characteristics quite accurately. The model predictions are verified against the 2-D numerical device simulator, DESSIS of ISE TCAD.     

Threshold voltage of narrow channel field effect transistors

A new effect associated with Metal-Oxide-Silicon Field-Effect-Transistors (MOS-FET's) is presented in this paper. MOS-FET's show an increase of threshold voltage with decreasing ratio of channel width to gate depletion width. This narrow channel effect is explained by means of geometrical edge effects. With decreasing channel width the transition from the field oxide depletion region to the gate oxide depletion region becomes comparable to the gate width and cannot be neglected in the derivation of the threshold voltage equation.A theoretical model is given to explain the influence of decreasing channel width on the threshold voltage as well as on other electrical parameters. This theoretical model is in good agreement with experimental results given in this paper.     

全耗尽SOI LDMOS阈值电压的解析模型

通过准二维的方法,求出了全耗尽SOILDMOS晶体管沟道耗尽区电势分布的表达式,并建立了相应的阈值电压模型。将计算结果与二维半导体器件模拟软件MEDICI的模拟结果相比较,两者误差较小,证明了本模型的正确性。从模型中可以容易地分析阈值电压与沟道浓度、长度、SOI硅膜层厚度以及栅氧化层厚度的关系,并且发现ΔVth与背栅压的大小无关。     

一种耗尽型短沟道MOS器件阈电压模型

本文研究了耗尽型MOS器件的短沟道效应,把Yau的电荷分配理论推广到耗尽型器件,并作了适当修正。提出一种简单而精确的耗尽型短沟道MOS器件阈电压分析模型,与实验数据吻合良好。该模型可以应用于这类器件及电路的CAD。     

Two-dimensional numerical analysis of the narrow gate effect in MOSFET

Lateral variation of the local threshold voltage causes non-linearity in the drain conductance-gate voltage characteristics, resulting in a nonunique external threshold voltage which varies with gate voltage. Using a 16-bit minicomputer, a two-dimensional (2-D) finite-difference program for narrow gate MOSFET (NAROMOS), and an accurate and efficient new finite-difference boundary equation at the oxide-semiconductor interface, computations are carried out for the external threshold voltage and a measurable electrical channel width as a function of the applied dc gate and substrate voltages. The depletion approximation is employed in order to compare the 2-D results with the 1-D analytical solution of the depletion model. Computed curves are presented for the lateral variations of the depletion layer thickness, surface potential, normal surface electric field, local as well as external threshold voltages, and electrical channel width as a function of the device structure, material parameters, and bias voltages. Based on the 2-D results and device physics, an analytical approximation of the threshold voltage versus the gate width, simple enough for CAD of VLSI, is derived whose parameters may be determined from either a 2-D computation or experimental measurements on one test device of a known gate width. The computed increase of the external threshold voltage with decreasing gate width compares well with published experimental data.     

Improved analytical model of surface potential with modified boundary conditions for double gate tunnel FETs

In this paper, an improved analytical model of the channel surface potential in the tunnel field effect transistors is established with modified boundary conditions considering the source and drain depletion widths, avoiding the deviation of the channel potential and the overestimate on the electric field. Based on the proposed surface potential model, the threshold voltage model is also developed with the transconductance change method. The influences of the channel and oxide structures on surface potential and threshold voltage are investigated. The good agreement is obtained by the comparison of the modeling results with the numerical simulation results, verifying the validation of the proposed model, and it also implied that this model will be helpful for the further investigation of TFETs.     

Inverse-narrow-width effects and small-geometry MOSFET thresholdvoltage model

An analytical threshold voltage model is developed based on the results from a three-dimensional MOSFET simulator, called MICROMOS. The model is derived by solving Poisson's equation analytically and is used to predict the threshold voltage of MOSFETs with fully recessed oxide isolation (the trench structure). Coupling was observed between the short-channel effect and the inverse-narrow-width effect. The coupling results from the mutual modulation of the depletion depth and is used to extend the analytical inverse narrow-width model to small-geometry devices. The model is compared with experimental data obtained from the literature as well as with the three-dimensional simulator. Satisfactory agreement for channel length down to 1.5 μm and channel widths down to 1 μm has been obtained     

A simple analytical model for the electrical characteristics of depletion-mode MOSFET's with application to low-temperature operation

A simple analytical model for depletion-mode MOSFET's is developed based on the gradual channel approximation and taking into account carrier freeze-out onto impurity sites implanted for threshold voltage modification. Theory is found to be in reasonable agreement with experimental results for n-channel depletion-mode MOSFET's at room temperature and at 77 K. It is shown that the common methods used for enhancement-mode devices to determine carrier channel mobility and threshold voltage, respectively, from the slope and voltage intercept of the current-gate voltage characteristics are invalid for depletion-mode devices. By comparison of enhancement and depletion devices on the same chip, it is shown that the processes associated with ion implantation had no effect on electron channel mobility at room temperature and caused at most a 25-percent reduction at 77 K. The model also is applicable to buried p-channel devices as used in CMOS technologies.     

GaAs OPFET characteristics considering the effect of gate depletionwith modulation due to incident radiation

A realistic analytical model of an ion-implanted GaAs OPFET has been presented. Both the photogeneration and photovoltaic effect and the voltage dependence of the depletion layer widths in the active region have been considered. The threshold voltage decreases in the enhancement device and increases in the depletion device at a particular dose, flux density, and trap center density when both the photovoltaic effect and photogeneration are taken into account compared to the case where the photovoltaic effect is ignored. At higher flux density and trap density, the threshold voltage shows a nonlinear effect at a lower value of the implanted dose, which is mainly due to the recombination term. The drain-source current significantly increases due to the photovoltaic effect because of the widening of the channel region. The device is pinched off at a higher drain-source voltage compared to the photogeneration case only