Designing power supply clamps for electrostatic discharge protection of integrated circuits

Power supply electrostatic discharge (ESD) clamping is needed to protect the IC power supply as well as to provide convenient discharge paths for ESD currents, and thereby simplify the total design problem. A variety of methods are reviewed and explored, notably those employing diodes or field effect transistor (FETs) built in bulk complementary metal-oxide semiconductor (CMOS) technology and avoiding avalanche behavior. Power clamping can occur across comparable power supplies or between a power supply and ground; there are diode and FET methods for each. Designs extend to clamping for mixed voltage supplies on a single chip, including power supplies above the gate oxide tolerance. New designs and results for power clamps based on PMOS FETs are presented for the first time.     

Low power CMOS level shifters by bootstrapping technique

A level shifter circuit using bootstrapped gate drive to minimise voltage swing is presented. Capacitors are used to maintain the voltage difference between the gates of pull-up PMOS and pull-down NMOS. The power saving over conventional level shifter is typically 50% for a 5 V input and 12 V output     

一种低电压、高增益电荷泵

电荷泵在低压电路中扮演着重要的角色。作为片上电荷泵,其面临的主要问题是:电压增益、电压纹波和面积效率。该文提出了一种新型的电荷泵电路,它采用辅助电荷泵、电平转移电路结构来产生不同摆幅的时钟,该时钟被用来驱动开关管的栅极,以有效控制开关管的电导,提高电压增益。由于采用PMOS管作为开关管,传输过程中避免了阈值电压损失。仿真结果显示,与以往文献中提到的电荷泵结构相比,该电荷泵具有更高的电压增益,开启时间短,纹波小,在低压应用环境优势更为突出。     

Threshold voltage-minimum gate length trade-off in buried channelPMOS devices for scaled supply voltage CMOS technologies

The trade-off between threshold voltage (V_th) and the minimum gate length (L_min) is discussed for optimizing the performance of buried channel PMOS transistors for low voltage/low power high-speed digital CMOS circuits. In a low supply voltage CMOS technology it is desirable to scale V_th and L_min for improved circuit performance. However, these two parameters cannot be scaled independently due to the channel punch-through effect. Statistical process/device modeling, split lot experiments, circuit simulations, and measurements are performed to optimize the PMOS transistor current drive and CMOS circuit speed. We show that trading PMOS transistor V_th for a smaller L_min results in faster circuits for low supply voltage (3.3 to 1.8 V) n⁺-polysilicon gate CMOS technology, Circuit simulation and measurements are performed in this study. Approximate empirical expressions are given for the optimum buried channel PMOS transistor V _th for minimizing CMOS circuit speed for cases involving: (1) constant capacitive load and (2) load capacitance proportional to MOS gate capacitance. The results of the numerical exercise are applied to the centering of device parameters of a 0.5 μm 3.3 V CMOS technology that (a) matches the speed of our 0.5 μm 5 V CMOS technology, and (b) achieves good performance down to 1.8 V power supply. For this process the optimum PMOS transistor V_th (absolute value) is approximately 0.85-0.90 V     

Flexible nano-hybrid inverter based on inkjet-printed organic and 2D multilayer MoS2 thin film transistor

We report a novel platform on which we design a flexible high-performance complementary metal–oxide–semiconductor (CMOS) inverter based on an inkjet-printed polymer PMOS and a two-dimensional (2D) multilayer molybdenum disulfide (MoS₂) NMOS on a flexible substrate. The initial implementation of a hybrid complementary inverter, comprised of 2D MoS₂ NMOS and polymer PMOS on a flexible substrate, demonstrates a compelling new pathway to practical logic gates for digital circuits, achieving extremely low power consumption with low sub-1 nA leakage currents, high performance with a voltage gain of 35 at 12 V supply voltage, and high noise margin (larger than 3 V at 12 V supply voltage) with low processing costs. These results suggest that inkjet-printed organic thin film transistors and 2D multilayer semiconducting transistors may form the basis for potential future high performance and large area flexible integrated circuitry applications.     

Power-efficient gate control of synchronous boost converters with high output voltage

A half output voltage swing gate driving scheme is presented for high voltage single chip DC/DC converters. In the proposed scheme the energy for the PMOS gate drive is reused for the NMOS gate drive, and switching loss is reduced. A high speed and area-efficient high voltage level shifter is also realised. A prototype is implemented using a 0.5 mum 40 V power BiCMOS process     

A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cellwith PMOS access transistors

While an ECL-CMOS SRAM can achieve both ultra high speed and high density, it consumes a lot of power and cannot be applied to low power supply voltage applications. This paper describes an NTL (Non Threshold Logic)-CMOS SRAM macro that consists of a PMOS access transistor CMOS memory cell, an NTL decoder with an on-chip voltage generator, and an automatic bit line signal voltage swing controller. A 32 Kb SRAM macro, which achieves a 1 ns access time at 2.5 V power supply and consumes a mere 1 W, has been developed on a 0.4 μm BiCMOS technology     

Feedback FET logic: a robust, high-speed low-power GaAs logicfamily

Feedback FET logic (FFL) with a special output stage that enables it to drive high on-chip capacitances with low power is discussed. FFL is robust in the face of process and temperature variations. The basic FFL gate is a NOR, but complex gates such as AND-OR-NOT are also practical. FFL is two to four times faster than comparable GaAs direct-coupled FET logic and Si CMOS and Si BiCMOS when driving on-chip capacitances that are typical of large ICs. FFL power at 200 MHz is also lower than CMOS and BiCMOS power by a factor of 2 to 4     

GaAs trickle transistor dynamic logic

A GaAs dynamic logic gate is proposed which uses a trickle transistor to compensate for leakage from the precharged node. This trickle transistor dynamic logic (TTDL) circuit is configured as a domino logic gate and a differential cascode voltage switch logic (CVSL) gate. Delay chains were implemented in a 1-μm GaAs enhancement/depletion (E/D) process where the depletion-mode FETs (DFETs) and the enhancement-mode FETs (EFETs) have threshold voltages of -0.6 and 0.15 V, respectively, in order to obtain an experimental characterization of these gates. In addition, the TTDL gates were used to implement a 4-b carry-lookahead adder. The adder has a critical delay of 0.8 ns and a power dissipation of 130 mW     

Electrical overstress due to ESD induced displacement currents

In this paper a new failure mode is introduced, which is related to the large dV/dt of ESD pulses. It was observed after +4 kV HBM stress for a 90V-BCD technology device and resulted in a gate oxide defect of a low voltage PMOS transistor, which was hidden deeper in the IC's circuitry. The underlying failure mechanisms are discussed based on experimental and simulational findings and measures for early identification and protection of potentially sensible devices are proposed.     

Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages

Usage of dual supply voltages in a digital circuit is an effective way of reducing the dynamic power consumption due to the quadratic relation of supply voltage to dynamic power consumption. But the need for level shifters when a low voltage gate drives a high voltage gate has been a limiting factor preventing widespread usage of dual supply voltages in digital circuit design. The overhead of level shifters forces designers to increase the granularity of dual voltage assignment, reducing the maximum obtainable savings. We propose a method of incorporating voltage level conversion into regular CMOS gates by using a second threshold voltage. Proposed level shifter design makes it possible to apply dual supply voltages at gate level granularity with much less overhead compared to traditional level shifters. We modify the threshold voltage of the high voltage gates that are driven by low voltage gates in order to obtain the level shifting operation together with the logic operation. Using our method, we obtained an average of 20% energy savings for ISCAS'85 benchmark circuits designed using 180-nm technology and 17% when 70-nm technology is used.     

A 9-ns 1-Mbit CMOS SRAM

A 1-Mbit CMOS static RAM (SRAM) with a typical address access time of 9 ns has been developed. A high-speed sense amplifier circuit, consisting of a three-stage PMOS cross-coupled sense amplifier with a CMOS preamplifier, is the key to the fast access time. A parallel-word-access redundancy architecture, which causes no access time penalty, was also incorporated. A polysilicon PMOS load memory cell, which had a large on-current-to-off-current ratio, gave a much lower soft-error rate than a conventional high-resistance polysilicon load cell. The 1-Mbit SRAM, fabricated using a half-micrometer, triple-poly, and double-metal CMOS technology, operated at a single supply voltage of 5 V. An on-chip power supply converter was incorporated in the SRAM to supply a partial internal supply voltage of 4 V to the high-performance half-micrometer MOS transistors.<>     

Improving ESD protection of 5 V NMOSFET large array device in 0.4 μm BCD process

In the output stage of power ICs, large array devices (LAD) of MOSFETs are usually used to drive a considerable amount of current. Electrostatic discharge (ESD) self-protection capability of LAD is also required. ESD layout rules are usually adopted in low voltage CMOS transistors to improve the ESD performance but with a large layout area. In this paper, a modified RC gate-driven circuit with gate signal control circuit is developed to keep the minimum device layout rule while achieving ESD self-protection. Thus, it results in a very small layout area increment while keeps the LAD operates safely in normal operation and gains good ESD protection level.     

一种应用于高压电机驱动的电平移位电路

针对传统电平移位电路输出电压范围不理想和不稳定的缺点,设计了一种具有高稳定性、低功耗的两级电平移位电路。该电路第一级采用固定偏置电流结构,消除NMOS与PMOS电学参数的依赖性并提高稳定性。通过引入扩宽输出电压范围的第二级电路结构,为高端PMOS提供可靠的栅驱动电压。仿真结果表明,所设计的电平移位电路实现了低压转高压功能,且输出范围满足高边栅驱动要求。该电路能较好地应用于高压电机驱动电路,实现单极性和双极性两种驱动控制。     

Improvement in threshold voltage control by minimizing boronpenetration in a LV-GCMOS technology

Maintaining tight threshold voltage (V_T) control for a low-voltage CMOS process is critical due to the large impact of V_T on circuit performance at low power supply voltages. In this paper, PMOS V_T was shown to be sensitive to poly gate thickness and BF₂⁺ source/drain implant energy. This data helped identify boron penetration as a prime contributor to PMOS threshold voltage variation. SIMS measurements were used to investigate boron diffusion through the poly gate at various stages in the process flow. These SIMS profiles pointed to the low-temperature thermal cycle of the nitride spacer deposition as a key step which influenced the amount of boron penetration and thus the final device threshold voltage. Experimental evidence shows that the temperature gradient across the nitride spacer deposition furnace causes a variable amount of boron penetration resulting in a large variation in PMOS V_T. We adopted a process flow change which virtually eliminated boron penetration and significantly reduced the sensitivity of the devices to manufacturing variations. Threshold voltage variation was reduced by a factor of two     

一个LVTSCR并联PMOS的高维持电压ESD防护器件

为了在5 V片上输入输出端进行静电放电(ESD)防护,提出了一种新型的LVTSCR结构。使用Silvaco 2D TCAD软件对此器件进行包含电学及热学特性的仿真。此新型器件交换了LVTSCR中N-Well的N+、P+掺杂区并引入了一个类PMOS结构用来在LVTSCR工作前释放ESD电流。器件仿真结果显示,与LVTSCR相比,该器件获得了更高的维持电压(10.51 V),以及更高的开启速度(1.05×10-10 s),同时触发电压仅仅从12.45 V增加到15.35 V。并且,如果加入的PMOS结构选择与NMOS相同的沟道长度,器件不会引起热失效问题。     

Power Si-MOSFET operating with high efficiency under low supply voltage

A design method for RF power Si-MOSFETs suitable for low-voltage operation with high power-added efficiency is presented. In our experiments, supply voltages from 1 V to 3 V are examined. As the supply voltage is decreased, degradation of transconductance also takes place. However, this problem is overcome, even at extremely low supply voltages, by adopting a short gate length and also increasing the N/sup -/ extension impurity concentration-which determines the source-drain breakdown voltage (V/sub dss/)-and thinning the gate oxide-which determines the TDDB between gate and drain. Additionally, in order to reduce gate resistance, the Co-salicide process is adopted instead of metal gates. With salicide gates, a 0.2 /spl mu/m gate length is easily achieved by poly Si RIE etching, while if metal gates were chosen, the metal film itself would have to be etched by RIE and it would be difficult to achieve such a small gate length. Although the resistance of a Co-salicided gate is higher than that of metal gate, there is no evidence of a difference in power-added efficiency when the finger length is below 100 /spl mu/m. It is demonstrated that 0.2 /spl mu/m gate length Co-salicided Si MOSFETs can achieve a high power-added efficiency of more than 50% in 2 GHz RF operation with an adequate breakdown voltage (V/sub dss/). In particular, an efficiency of more than 50% was confirmed at the very low supply voltage of 1.0 V, as well as at higher supply voltages such as 2 V and 3 V. Small gate length Co-salicided Si-MOSFETs are a good candidate for low-voltage, high-efficiency RF power circuits operating in the 2 GHz range.     

A floating-gate analog memory device for neural networks

A floating-gate MOSFET device that can be used as a precision analog memory for neural network LSIs is described. This device has two floating gates. One is a charge-injection gate with a Fowler-Nordheim tunnel junction, and the other is a charge-storage gate that operates as a MOSFET floating gate. The gates are connected by high resistance, and the charge-injection gate is small so that its capacitance is much less than that of the charge-storage gate. By applying control pulses to the charge-injection gate, it is possible to charge and discharge the MOSFET floating gate in order to modify the MOSFET current with high resolution over 10 b. The charge injection can be carried out without disturbing the MOSFET output current with high voltage control pulses. This device is useful for on-chip learning in analog neural network LSIs     

A gate-coupled PTLSCR/NTLSCR ESD protection circuit fordeep-submicron low-voltage CMOS ICs

A novel electrostatic discharge (ESD) protection circuit, which combines complementary low-voltage-triggered lateral SCR (LVTSCR) devices and the gate-coupling technique, is proposed to effectively protect the thinner gate oxide of deep submicron CMOS ICs without adding an extra ESD-implant mask. Gate-coupling technique is used to couple the ESD-transient voltage to the gates of the PMOS-triggered/NMOS-triggered lateral silicon controlled rectifier (SCR) (PTLSCR/NTLSCR) devices to turn on the lateral SCR devices during an ESD stress. The trigger voltage of gate-coupled lateral SCR devices can be significantly reduced by the coupling capacitor. Thus, the thinner gate oxide of the input buffers in deep-submicron low-voltage CMOS ICs can be fully protected against ESD damage. Experimental results have verified that this proposed ESD protection circuit with a trigger voltage about 7 V can provide 4.8 (3.3) times human-body-model (HBM) [machine-model (MM)] ESD failure levels while occupying 47% of layout area, as compared with a conventional CMOS ESD protection circuit     

Simultaneous switching noise in on-chip CMOS power distribution networks

Simultaneous switching noise (SSN) has become an important issue in the design of the internal on-chip power distribution networks in current very large scale integration/ultra large scale integration (VLSI/ULSI) circuits. An inductive model is used to characterize the power supply rails when a transient current is generated by simultaneously switching the on-chip registers and logic gates in a synchronous CMOS VLSI/ULSI circuit. An analytical expression characterizing the SSN voltage is presented here based on a lumped inductive-resistive-capacitive RLC model. The peak value of the SSN voltage based on this analytical expression is within 10% as compared to SPICE simulations. Design constraints at both the circuit and layout levels are also discussed based on minimizing the effects of the peak value of the SSN voltage.