Analysis and design of LC oscillators associated with frequency multipliers: a phase noise perspective

When a local oscillator signal generation system is based on an LC oscillator and a frequency multiplier, the question of determining the optimal multiplication factor is a key issue. In this paper, the problem is addressed in order to minimize the 1/f ² phase noise within a tuning range constraint. The analysis, with a practical graphical representation, reveals the oscillator phase noise dependence on the oscillating frequency in the transition from two different regimes, named the inductor‐limited quality factor and the capacitor‐limited quality factor. The results obtained enable the evaluation of the phase noise performance of systems based on a sub‐harmonic and super‐harmonic oscillators and how they compare with an oscillator in the fundamental mode. Crucial questions like the phase noise improvement that these systems can achieve are analytically answered. A design methodology is thus proposed and verified through measurements on a frequency source at 31 GHz, composed by a sub‐harmonic voltage‐controlled oscillator followed by an injection‐locked frequency tripler, dedicated to backhauling applications, designed on a BiCMOS process technology. The tuning range is 10%, and the phase noise at a 1‐MHz offset is −112 dBc/Hz. Copyright © 2017 John Wiley & Sons, Ltd.     

A 4.8–6.8 GHz low phase noise LC VCO in 0.13‐µm CMOS technology

This letter presents a novel LC voltage controlled oscillator (VCO) supporting the high‐speed serial transmission standard of RapidIO in 0.13‐µm complementary metal‐oxide semiconductor technology. The low phase noise is achieved through several techniques including current source switching, parallel coupled negative transconductance cell, and varactor bias combination scheme. Measured results of proposed circuit show a low phase noise of ?120 dBc/Hz at 1 MHz offset from 6.25 GHz carrier and tuning range of 4.8 ~ 6.8 GHz (34.48%) while consuming 7.4 mW under the supply voltage of 1.2 V. Copyright © 2015 John Wiley & Sons, Ltd.     

Low‐power quadrature generators for body area network applications

This paper presents different alternatives for the implementation of low‐power monolithic oscillators for wireless body area networks and describes the design of two quadrature generators operating in the 2.4‐GHz frequency range. Both implementations have been designed in a 90‐nm Complementary Metal‐Oxide Semiconductor (CMOS) technology and operate at 1 V of supply voltage. The first architecture uses a voltage‐controlled oscillator (VCO) running at twice the desired output frequency followed by a divider‐by‐2 circuit. It experimentally consumes 335 μW and achieves a phase noise of ?110.2 dBc/Hz at 1 MHz. The second architecture is a quadrature VCO that uses reinforced concrete phase shifters in the coupling path for phase noise improvement. Its power consumption is only 210 μW, and it obtains a phase noise of ?111.9 dBc/Hz at 1 MHz. Copyright © 2011 John Wiley & Sons, Ltd.     

67 GHz three‐spiral transformer CMOS oscillator

This paper presents a 67GHz LC oscillator exploiting a three‐spiral transformer and implemented in 65nm bulk complementary metal–oxide–semiconductor technology by STMicroelectronics. The three‐spiral transformer allows operating with a lower voltage supply, still obtaining good phase noise performance, and achieving a compact design. Measured performances when supplied with 1.2 V are: oscillation frequency of 67 GHz, phase noise (PN) equal to ?96 dBc/Hz at 1 MHz frequency offset from the carrier, power consumption (P_C) equal to 19.2 mW and figure of merit (FOM) equal to ?179.7 dB/Hz. Measured performances when supplied with 0.6 V are: oscillation frequency of 67 GHz; PN equal to ?88.7 dBc/Hz at a 1 MHz frequency offset from the carrier; P_C equal to 3.6 mW and FOM equal to ?179.7 dB/Hz. Copyright © 2016 John Wiley & Sons, Ltd.     

Sinusoidal shaping of the ISF in LC oscillators

A new method to decrease the phase noise of the sinusoidal oscillators is proposed. The proposed method is based on using a dynamic transistor biasing in a typical oscillator topology. This method uses the oscillator impulse sensitivity function (ISF) shaping to reduce the sensitivity of the oscillator to the transistor noise and as a result reducing the oscillator phase noise. A 1.8 GHz, 1.8 V designed oscillator based on the proposed method shows a phase noise of ?130.3dBc/Hz at 1 MHz offset frequency, thereby showing about 6 dB phase noise decreasing in comparison with the typical constant bias topology. This result is obtained from the simulation based on 0.18u CMOS technology and on‐chip spiral inductor with a quality factor equal to 8. Copyright © 2007 John Wiley & Sons, Ltd.     

LC‐active VCO for CMOS RF transceivers

A novel fully integrated CMOS LC tank VCO is presented. The LC tanks are implemented by exploiting the active circuit ‘boot‐strapped inductor’ (BSI), which behaves like a high‐quality factor inductor. Particularly, the LC tanks have been implemented by introducing a new version of the CMOS BSI circuit, which provides better versatility and design reliability. In order to verify the effectiveness of such an approach, a case study for 5–6 GHz direct‐conversion multi‐standard WLAN transceivers is presented. The VCO has been designed in a 0.35µm standard CMOS technology. The new BSI exhibits a high‐quality factor (higher than 25 over the all frequency range) and provides a high selectivity without introducing a relevant excess of noise, for a better spectral purity and a lower phase noise (PN) of the VCO. The overall VCO circuit consumes 9 mW. The VCO produces an oscillation in the tuning range from 4.91 to 5.93 GHz (nearly equal to 19%). The circuit exhibits a PN of ?129dBc/Hz at 1 MHz of frequency offset from the central frequency (5.4 GHz) and a FOM equal to 189.5 dBc/Hz at 100 kHz and 194.1 dBc/Hz at 1 MHz of frequency offset, respectively. Copyright © 2009 John Wiley & Sons, Ltd.     

A common‐mode replica compensated inductor–capacitor voltage‐controlled oscillator for mixed‐signal system‐on‐chip applications

A novel 1.57 GHz complementary metal–oxide semiconductor inductor–capacitor voltage‐controlled oscillator with the common‐mode replica compensation is introduced for mixed‐signal system‐on‐chip applications. In order to alleviate power line disturbances, the center tap node of differential symmetric inductor and the replica biasing circuit are adopted in the differential voltage regulating unit to reduce power supply sensitivity. In addition, this proposed design also leads to low tuning gain and low power dissipation. The post‐layout simulation results under the Taiwan Semiconductor Manufacturing Company's mixed‐signal 0.18 µm 1P6M process show that the proposed design achieves power supply rejection of ?68.6 dB at low frequencies and 1.2 MHz/V pushing sensitivity. It exhibits phase noise of ?130.6 dBc/Hz at a 1 MHz offset from a 1.57 GHz carrier yet dissipates only 5.58 mW under a 1.8 V power supply. Copyright © 2011 John Wiley & Sons, Ltd.     

A wideband low‐spur 0.18‐µm CMOS phase‐locked loop with bandwidth calibration

This paper presents a 0.18‐µm complementary metal‐oxide‐semiconductor wideband phase‐locked loop with low reference spurs. The dual‐level charge‐pump current calibration technique is proposed to maintain a constant loop bandwidth for wide operation frequency range and achieve low reference spurs. The first level charge‐pump current calibration is seamlessly incorporated in the automatic frequency band hopping control and the mechanism also ensures enough negative transconductance for the voltage‐controlled oscillator to function throughout the whole frequency range. The charge‐pump current mismatch is calibrated by the second level charge‐pump current calibration combined with the pulse‐width scaling technique. The operation frequency range of the phase‐locked loop covers from 4.7 GHz to 6.1 GHz. The measured phase noise is?116 dBc/Hz at 1‐MHz offset and the reference spurs are below?66.8 dBc. Copyright © 2015 John Wiley & Sons, Ltd.     

Increasing power efficiency in the design of a low power and low phase noise CMOS LC oscillator

This study developed a local oscillator (LO) with low phase noise and low power consumption. The proposed oscillator core comprises a pair of cross‐coupled transistors, which are fed by another pair of transistors that injects current at moments close to the peak of output voltage. The position of the current injection transistors, which are inserted in series with the cross‐coupled transistors, affects the waveform of current injected into an inductive–capacitive (LC) tank. Installing a capacitor on the source node of the cross‐coupled transistors increases the current injected into the LC tank and thereby augments the output voltage amplitude and power efficiency of the LO. The resonator phase shift and Q can be corrected by adjusting the source capacitance, which filters noise. These changes reduce the phase noise to ?123.4 dBc/Hz at a frequency offset of 1 MHz and improve oscillator performance with a figure of merit equal to ?193.5 dBc/Hz. To evaluate the LC tank, a 5 GHz LO was simulated at 1.8 V power supply and 2.5 mW power consumption. The simulation was conducted using a practical 0.18 complementary metal–oxide–semiconductor model manufactured by the Taiwan Semiconductor Manufacturing Company. The simulation results confirmed the analytical findings.     

基于ADF4002的低相噪取样本振设计

本文设计并实现了一种微波锁相环中取样器的本振电路,取样本振以频率合成芯片ADF4002为鉴相器,反馈通道采用内插混频器的结构,避免了单环通过简单倍频产生的相位噪声恶化。详细阐述了取样本振电路的实现方案和工作原理,并使用仿真软件对环路滤波器进行设计。通过实验测试,输出频率为214．815MHz时锁相环的相位噪声为：-137dBc／Hz@10kHz、-140dBc／Hz@100kHz,最大输出频率间隔1MHz,满足了取样本振的低相位噪声和高频率分辨率的要求。     

Design and analysis of differential ring voltage controlled oscillator for wide tuning range and low power applications

Voltage-controlled oscillator (VCO) is the most basic component required for all wireless and communication systems. In this article, a four-stage differential ring VCO with two control voltages for wide tuning range is proposed. This VCO uses the dual-delay loop technique for high operation frequency. Also, a low-V_T NMOS transistor is used in series with pull down network of the proposed VCO delay cell to achieve low frequencies. Prelayout simulation of the proposed VCO is performed in 65-nm TSMC CMOS technology in Cadence software under 1.2-V supply voltage. The tuning range of the proposed VCO varies from 1 MHz to 13.8 GHz and has been improved by 19.77% compared to other works. The power consumption of this low power VCO is between 29.3 μW to 1.715 mW. The phase noise of the proposed circuit is −82.3 dBc/Hz at 1 MHz offset frequency and −106.9 dBc/Hz at 10 MHz offset frequency from 5.161 GHz center frequency, while its area is 102.457 μm² . This design demonstrates other benefits in low power consumption and area compared with other ring oscillators.     

A 3.6‐mW 6‐GHz current‐reuse VCO‐buffer with improved load drivability in 65‐nm CMOS

A new current‐reuse voltage‐controlled oscillator (VCO)‐buffer with enhanced load drivability is proposed. It incorporates a PMOS‐based source follower stacked atop a NMOS‐based LC VCO to share the bias current, while preventing the voltage stress at any oscillation node from exceeding the 1.2‐V technology voltage limit. Also, ac‐coupling networks are avoided between the VCO and buffer, improving the Q of the LC tank while minimizing parasitics. With internal buffering, the VCO can directly drive up a 50‐Ω load for testing, or to withstand a large capacitive load in on‐chip local oscillator distribution, particularly suitable for multi‐band MIMO WLAN radios . The fabricated VCO‐buffer in 65‐nm CMOS measures 13.8% tuning range from 5.64 to 6.4 GHz, consumes 3.6 mW at 1.2 V and exhibits ?108.84 dBc/Hz phase noise at 1‐MHz offset. Copyright © 2013 John Wiley & Sons, Ltd.     

Design of a CMOS 65-nm inductor-less VCO for ISM applications in the VHF band

This paper presents a design of a CMOS cross-coupled voltage-controlled oscillator (VCO) using active inductors (AIs) for wide-band applications and can also be applied to various wireless technologies standards. The compatibility of this design to different wireless standards highlights its potential to be implemented at the core of the communication front end in the Internet of Things (IoT). The proposed AI design employs a gyrator-C topology as the basic structure to generate an inductance. The VCO uses a cross-coupled oscillator structure with a pair of varactors to sweep the frequency. Two extra capacitors, between the AIs and the outputs of the VCO core tank, are employed to enhance the performance of the phase noise and make the VCO work similarly to a linear transconductance (LiT) oscillator. Both the AIs and the VCO are designed in the TSMC 65-nm CMOS technology, and the performance is analyzed using postsimulation results, as well as through measurements. The fundamental frequency spans from 140 to 463 MHz. Thus, the relative tuning range of this design is approximately 107%. The optimal phase noise of the design is around −97 dBc/Hz at 1-MHz offset. Furthermore, it achieves an excellent figure of merit (FOM) around −163 dBc/Hz with a direct current (DC) power consumption less than 3 mW. The proposed design shows an advantage in phase noise and power consumption in comparison with previous active inductor VCO and ring VCO designs, respectively. The final layout occupies only 0.4 × 0.62 mm² including the pads. The proposed AI-VCO shows a compact size, linear tuning, low power consumption, and good phase noise performance.     

A high output power and low phase noise GaN HEMT VCO with array of switchable inductors

This paper presents cross‐coupled voltage‐controlled oscillators (VCOs) involving array of switchable inductors (i.e., N  = 1 and N  = 2 switchable inductors) and implemented using gallium‐nitride high electron mobility transistors on Si substrate technology for worldwide interoperability for microwave access applications. Band selection and coarse frequency tuning were achieved using the array of switchable inductors, whereas fine tuning was controlled using varactors. Two bands were obtained using the one‐stage switchable inductor VCO operating in the ranges 3.41–3.57 GHz and 3.85–3.94 GHz. The VCO output power (P_out) was 21.8 dBm at 3.57 GHz from a 10‐V power supply. Four continuous bands were obtained using the two‐stage switchable inductors VCO operating in the range of 3.16–3.4, 3.25–3.64, 3.48–3.71 and 3.64–3.9 GHz, respectively. An additional band was generated by fine‐tuning the inductance through mutual coupling between the transmission line and one of the inductors. The proposed two‐stage switchable inductors VCO provided a 21% tuning range at frequencies ranging with a control voltage ranging from 12 to 20 V, a low phase noise of −123 dBc/Hz at a 1‐MHz offset from a 3.3‐GHz carrier and a P_out of 21 dBm at 3.5 GHz from a 10‐V power supply. Copyright © 2017 John Wiley & Sons, Ltd.     

Fast settling frequency synthesizer with two‐point channel control paths

A frequency synthesizer with low‐power and very short settling time is introduced, which utilizes two‐point channel control paths. While the main‐path is the same as normal channel controls, a digital‐to‐analog converter (DAC) with tunable gain is used for the compensation‐path to form a feed‐forward direct voltage‐controlled oscillator (VCO) control path. When the two paths are ideally matched, the two‐point control can show zero settling time regardless of the amount of frequency change. However, the settling time performance can be significantly degraded if there exists any mismatch between the two paths. In order to remove the mismatch, a simple compensation method combining a linearized VCO with a resistor‐loaded tunable DAC is presented. We show that the overall mismatch can be effectively tuned out by controlling the DAC load resistor, since the mismatch caused by process–voltage–temperature variations is dominated by the resistor variation. We have achieved near‐zero settling time for 75thinspaceMHz frequency jumping from 2.4 GHz even with the use of narrow phase‐locked loop (PLL) bandwidth of 20 kHz. When the phase noise at 1 MHz offset from 2.4 GHz is ? 116.6dBc/ Hz, the total PLL power consumption using 0.18 µm CMOS technology is only 4.2 mW. Copyright © 2011 John Wiley & Sons, Ltd.     

An inductorless CMOS quadrature oscillator continuously tuneable from 3.1 to 10.6 GHz

Modern RF front‐ends require wide tuning‐range oscillators with quadrature outputs. In this paper we present a two‐integrator quadrature oscillator, which covers the whole bandwidth of UWB applications. A circuit prototype in a 130 nm CMOS technology is continuously tuneable from 3.1 to 10.6 GHz. The circuit die area is less than 0.013mm², leading to a figure‐of‐merit FOMA of ?176.7dBc/Hz at the upper frequency. The supply voltage is 1.2 V, and the power consumption is 7 mW at the lower frequency and 13 mW at the upper frequency. Copyright © 2010 John Wiley & Sons, Ltd.     

Low Phase Noise LC-VCO with Multi-Stage Filtering

A low-phase-noise CMOS voltage-controlled oscillator (VCO) with zero-bias scheme and multi-stage filtering is presented. Sharing ground with fully integrated loop filter, the PMOS-only VCO achieves a zero-bias scheme, which prevents tuning line noise from disturbing VCO output common-mode voltage and hence minimizes phase noise caused by nonlinear C-V characteristic of varactors. Top-biased current source is optimized by multi-stage filtering to reduce 1/f flicker and thermal noise. Fabricated in TSMC 180 nm CMOS process, the proposed VCO exhibits a measured oscillation frequency of 0.85~1.45 GHz, with a phase noise of -121.8~-131.3 dBc/Hz @1MHz offset over the whole band. Power consumption is 3.8~6.3mW from a 1.8V supply.     

Analyses and techniques for phase noise reduction in CMOS Colpitts oscillator topology

This paper reports the analyses of three techniques for phase noise reduction in the complementary metal‐oxide semiconductor (CMOS) Colpitts oscillator circuit topology. Namely, the three techniques are inductive degeneration, noise filter, and optimum current density. The design of the circuit topology is carried out in 28‐nm bulk CMOS technology. The analytical expression of the oscillation frequency is derived and validated through circuit simulations. Moreover, the theoretical analyses of the three techniques are carried out and verified by means of circuit simulations within a commercial design environment. The results obtained for the inductive degeneration and noise filter show the existence of an optimum inductance for minimum phase noise. The results obtained for the optimum bias current density technique applied to a Colpitts oscillator circuit topology incorporating either inductive degeneration or noise filter show the existence of an optimum bias current density for minimum phase noise. Overall, the analyses show that the adoption of these techniques may lead to a potential phase noise reduction up to 19 dB at a 1‐MHz frequency offset for an oscillation frequency of 10 GHz. © 2015 The Authors International Journal of Circuit Theory and Applications Published by John Wiley & Sons Ltd.     

Process variation compensation technique for voltage‐controlled ring oscillator

A voltage‐controlled ring oscillator with process variation compensation circuits is designed using 0.25 µm CMOS technology. The simulation results show that the proposed ring oscillator increases the guaranteed frequency tuning range by 12% compared to a conventional ring oscillator. Copyright © 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Survey of integrated‐circuit‐oscillator phase‐noise analysis

This tutorial distills the salient phase‐noise analysis concepts and key equations developed over the last 75 years relevant to integrated circuit oscillators. Oscillator phase and amplitude fluctuations have been studied since at least 1938 when Berstein solved the Fokker–Planck equations for the phase/amplitude distributions of a resonant oscillator. The principal contribution of this work is the organized, unified presentation of eclectic phase‐noise analysis techniques, facilitating their application to integrated circuit oscillator design. Furthermore, we demonstrate that all these methods boil down to obtaining three things: (1) noise modulation function; (2) noise transfer function; and (3) current‐controlled oscillator gain. For each method, this paper provides a short background explanation of the technique, a step‐by‐step procedure of how to apply the method to hand calculation/computer simulation, and a worked example to demonstrate how to analyze a practical oscillator circuit with that method. This survey article chiefly deals with phase‐noise analysis methods, so to restrict its scope, we limit our discussion to the following: (1) analyzing integrated circuit metal–oxide–semiconductor/bipolar junction transistor‐based LC, delay, and ring oscillator topologies; (2) considering a few oscillator harmonics in our analysis; (3) analyzing thermal/flicker intrinsic device‐noise sources rather than environmental/parametric noise/wander; (4) providing mainly qualitative amplitude‐noise discussions; and (5) omitting measurement methods/phase‐noise reduction techniques. Copyright © 2013 John Wiley & Sons, Ltd.