基于BDD的谓词分析与优化

为对带谓词的数据流进行准确而有效的分析,首先介绍了John W.Sias等人提出的一种基于二进制决策图(BDD)的谓词分析系统(PAS);然后在其基础上,提出了结合芯片自身体系结构特点的谓词优化算法。将PAS及优化算法在学院研制的FT_D4芯片的编译器上实现,实验结果表明,这种基于BDD的谓词分析与优化方法简化了程序控制结构,减少了对谓词寄存器的使用,缩短了代码执行时间,性能获得了较大的提高。     

谓词μ演算和模态图的语义一致性

模态图是谓词μ演算的一种有效的图形表示形式.证明了谓词μ演算和模态图的语义一致性,详细讨论了谓词μ演算公式、嵌套谓词等式系和模态图之间的关系,并给出了一种优化的从线性公式到嵌套谓词等式系的转换算法.     

基于程序行为特征比较的谓词切换排序

谓词切换（Predicate Switching）通过动态改变程序中的谓词判断语句状态观察程序运行结果的变化,分析可能与错误相关的关键谓词判断语句,从而实现辅助错误定位．谓词判断语句排序算法决定了谓词切换定位关键谓词判断语句的效率．已有的排序算法如LEFS算法定位效率较低;PRIOR算法虽然提高了定位效率,但必须首先做程序动态切片找寻与错误相关的谓词判断语句集合,而后建立程序依赖图以定义谓词判断语句的优先级,这个过程需要花费大量的时间,且算法复杂度较高．在这两种算法基础上提出一种新的改进排序算法,首先通过对比成功和失败的测试用例在运行中所展现出来不同程序行为特征,以此定义谓词判断语句的优先级,然后对不同优先级别的谓词根据执行先后顺序进行反向排序．基于基准测试集SiemensSuite的程序进行了实验,结果表明本文的排序算法与LEFS算法相比定位效率更高,与PRIOR算法相比减少定义谓词优先级的耗费,且算法更易于实现．     

基于谓词代码的编译优化技术研究

程序中大量分支指令的存在,严重制约了体系结构和编译器开发并行性的能力。有效发掘指令级并行性的一个主要挑战是要克服分支指令带来的限制。利用谓词执行可有效地删除分支,将分支指令转换为谓词代码,从而扩大了指令调度的范围并且删除了分支误测带来的性能损失。阐述了基于谓词代码的指令调度、软件流水、寄存器分配、指令归并等编译优化技术。设计并实现了一个基于谓词代码的指令调度算法。实验表明,对谓词代码进行编译优化,能有效提高指令并行度,缩短代码执行时间,提高程序性能。     

一种应用加权相容图的可测性寄存器分配算法

提出一种基于加权相容图的可测性寄存器分配模型,给出一个基于可测寄存器分配准则的相容图边的权值公式,并运用改进的加权团划分算法对加权相容图进行处理,从而实现了在寄存器分配过程中同时考虑4个可测性准则,达到提高设计可测性的目的.实验结果表明了算法在可测性方面的有效性.     

一阶谓词逻辑的图形推理法

针对已有一阶谓词逻辑推理方法中存在的推理效率低等问题,研究一种基于谓词/变迁系统的图形推理法。定义了描述谓词间与/或关系的谓词-与/或图,借助谓词-与/或图表示谓词/变迁系统,提出一种实现反向推理的目标制导的图形推理法。该方法推理效率高,较已有的推理方法具有一定的优越性。     

基于图模型的中文多谓词语义角色标注方法

针对语义角色标注中的多谓词现象,从图模型角度出发,提出一种中文多谓词语义角色标注方法。对句中的多个谓词进行联合语义分析,并采用随机爬山算法优化图模型。利用句中多个谓词之间的全局特征,提升语义角色的区分度。在中文命题库上的实验结果表明,该方法可以明显提高语义角色标注的分类效果。     

嵌入式处理器寄存器分配的一种混合演化算法

通用处理器的寄存器分配一般采用图着色的方法.除非考虑特例,优化的图着色是NP完全性问题.因此,传统寄存器分配常利用图着色的启发式算法,并能对规则的RISC处理器生成质量较高的代码.但由于嵌入式处理器不规则的体系结构特征,这种传统寄存器分配方法生成的代码质量不能满足嵌入式领域的要求.本文提出了一种新的遗传算法和局部搜索相混合的元启发式方法,能较好地克服传统寄存器分配的不足.实验结果表明,这种新的算法比传统图着色寄存器分配算法减少约30%spill代码.     

分片式处理器上的谓词执行技术优化

谓词执行能使分片式处理器充分利用众多的执行单元,开发指令级并行性.但因此形成的超块也使得分支误预测代价增大,所以提高分支预测器的性能至关重要.本文提出一种基于剖析信息决策的谓词执行技术,该技术利用剖析信息对谓词执行前后的执行周期进行估算,从而对分支的谓词执行进行决策.该技术使分支预测器的命中率提高了0.68%～3.50%,使系统性能提高了1.67%～8.33%.同时,利用select指令表示谓词化指令也消除了重命名阶段寄存器多定义问题.     

多寄存器组网络处理器上的寄存器分配技术

针对传统的图着色寄存器分配算法不能直接处理网络处理器的操作问题,提出了一种多寄存器组网络处理上的寄存器分配技术．在依次分析了一个符号寄存器可能位于哪些寄存器组？如果没有候选组,该如何解决这种冲突？如果有多个候选组,该选用哪个组等问题的基础上,通过将这些方法与图着色寄存器分配算法相融合,在IXP上实现了这种多寄存器组的寄存器分配,提高了它的可编程性．这种方法也可运用到其它具有类似寄存器结构的处理器上．     

基于同余方程和改进的压扁控制流的混淆算法

针对现有控制流混淆算法的混淆结果单一的问题,提出了一种基于同余方程和改进的压扁控制流混淆算法。首先,使用密钥和一组同余方程来生成源代码的基本块中需要使用的不透明谓词;其次,基于Logistic混沌映射提出了一种新的N态不透明谓词构造算法,并将其应用到现有的压扁控制流算法中,对现有的压扁控制流算法进行改进;最后,将上述两个对源码进行混淆的算法结合,以此来增加源代码中控制流的复杂度,使其更难被破解。与现有的基于混沌不透明谓词的压扁控制流算法相比,所提混淆算法使混淆后代码的防篡改攻击时间平均提高了22%以上,总圈复杂度平均提高了34%以上。实验结果表明,所提算法能够保证混淆后程序执行结果的正确性并且具有很高的圈复杂度,能够有效地抵抗静态攻击和动态攻击。     

类PSO算法对DSP偏移分配问题的优化

用C语言编写DSP软件时,优化设计尤为重要。近年来提出了多种针对DSP代码生成阶段的偏移分配优化算法,这些算法通过调整局部变量在存储器中的布局来提高变量地址的计算效率。该文提出一种将微粒群算法与遗传算法相结合的算法(类PSO算法),对变量访问序列中各变量地址的分配进行优化,使计算地址所需的代码数量最小,从而减少程序的运行时间,提高DSP的工作效率。     

Floating accumulator architecture

Although technology advancement can pack more and more physical registers in processors, the numbers of architectural registers defined by the instruction set architectures (ISAs) remain relatively small on most modern processors. Exposing more architectural registers to compilers and programmers can improve the effectiveness of compiler optimization and the quality of code. However, increasing the number of architectural registers by simply adding extra bits to the register fields of instructions will expand the code size. Therefore, a better way of exposing more ISA registers without significantly expanding the code size is needed. This paper presents a new ISA called Floating Accumulator Architecture (FAA) that can expand the number of ISA registers without increasing the instruction length. Unlike the accumulator architecture whose accumulator is a fixed, special register, FAA dynamically chooses a register from the general-purpose register file as the accumulator. In other words, the accumulator in FAA is an alias to some register in the register file at any instruction, and the alias relation can be dynamically updated by FAA at any program points. Since the accumulator implicitly stores the result, the destination register field can be omitted from FAA instructions, resulting in a saving of 3 to 5 bits for each instruction. This new free instruction bit space can be utilized in two possible ways: doubling the number of ISA registers of modern 32-bit RISC processors or maintaining the number of ISA registers for 16-bit instructions on embedded processors. This paper presents the result of utilizing the free bit space to double the number of ISA registers from 16 to 32 on ARM processors, and experimental results show that performance can be improved by 7.6% on average for MediaBench benchmarks.     

一种流加密方案的设计与分析*

利用离散Hopfield神经网络对多个线性反馈移位寄存器（LFSR）的非线性选择输出,提出了一种强度较高的序列加密系统。安全性分析与仿真验证表明,该算法构造的伪随机序列具有大周期性、平衡性、相关免疫性等特点,满足密码学的要求。     

On the Sethi-Ullman algorithm

A directed acyclic graph (dag) can be used to represent an arithmetic expression consisting of sequences of binary operations on arguments. The Sethi-Ullman algorithm (Journal of the ACM, Vol. 17 No. 4, pp. 715-728) generates optimal object code for a machine with N≧1 registers and unlimited memory capacity when the dag is a binary tree.

We first describe a dag labeling algorithm which gives the minimum number of registers required to evaluate any node without any stores.

We then define a subclass of dags, the 1-load binary dags, employing a tree-like grammar, and modify the Sethi-Ullman algorithm to include this subclass but only when N = 2 registers. The proof of optimality relies on the use of syntax directed translation schemas. Modification of the algorithm to include all dags, or to allow N > 2 registers, appears difficult.     

Solving the Register Allocation Problem for Embedded Systems Using a Hybrid Evolutionary Algorithm

Embedded systems are unique in the challenges they present to application programmers, such as power and memory space constraints. These characteristics make it imperative to design customized compiler passes. One of the important factors that shape runtime performance of a given embedded code is the register allocation phase of compilation. It is crucial to provide aggressive and sophisticated register allocators for embedded devices, where the excessive compilation time can be tolerated due to high demand on code quality. Failing to do a good job on allocating variables to registers (i.e., determining the set of variables to be stored in the limited number of registers) can have serious power, performance, and code size consequences. This paper explores the possibility of employing a hybrid evolutionary algorithm for register allocation problem in embedded systems. The proposed solution combines genetic algorithms with a local search technique. The algorithm exploits a novel, highly specialized crossover operator that takes into account domain-specific information. The results from our implementation based on synthetic benchmarks and routines that are extracted from well-known benchmark suites clearly show that the proposed approach is very successful in allocating registers to variables. In addition, our experimental evaluation also indicates that it outperforms a state-of-the-art register allocation heuristic based on graph coloring for most of the cases experimented.     

Timing Error Aware Register Allocation in TS

Timing speculative (TS) architecture is promising for improving the energy efficiency of microprocessors. Error recovery units, designed for tolerating occasional timing errors, have been used to support a wider range of voltage scaling, therefore to achieve a better energy efficiency. More specifically, the timing error rate, influenced mainly by data forwarding, is the bottleneck for voltage down-scaling in TS processors. In this paper, a new Timing Error Aware Register Allocation method is proposed. First, we designed the Dependency aware Interference Graph (DIG) construction to get the information of Read after Write (RAW) in programs. To build the construction, we get the disassemble code as input and suppose that there are unlimited registers, the same way as so-called virtual registers in many compilers. Then we change the disassemble codes to the SSA form for each basic block to make sure the registers are defined only once. Based on the DIG construction, registers were reallocated to eliminate the timing error, by loosening the RAW dependencies. We construct the DIG for each function of the program and sort the edge of DIG by an increasing weight order. Since a smaller weighted-edge value means that its owner nodes have more frequent access in instruction flows, we expect it in different registers with no read-write dependency. At the same time, we make sure that there are no additional new spill codes emerging in our algorithm to minimize the rate of spill code. A high rate of spill code will not only decrease the performance of the system but also increase the unexpected read-write dependency. Next, we reallocate the registers by weight order in turn to loosen the RAW dependencies. Furthermore, we use the NOP operation to pad the instructions with a minimal distance value of 2. Experiment results showed that the average distance of RAW dependencies was increased by over 20%.     

机器语言的类型化及代码的安全检查

根据类型系统思想，为Intel／x86体系结构的机器语言重新定义了类型表达式并建立一套类型系统，机器语言代码虽然是一种无类型的二进制编码，但其类型信息被隐含在指令的操作语义中，利用建立在类型系统基础之上的类型推理算法可以静态地推理机器代码的安全性，由于所讨论的机器语言包含了跳转、函数调用和返回等主要指令，因此，这种静态检查方法可广泛应用于其他体系结构的低级语言代码的检查中。     

一种基于剪切的SLP向量化方法*

作为多媒体和科学计算等领域重要的程序加速器件之一,SIMD扩展部件现已广泛集成于各类处理器中。自动向量化方法是目前生成SIMD向量化程序的重要手段,超字并行SLP (Superword Level Parallelism)方法现已广泛应用于编译器中,并成为实现基本块级代码向量化的主要手段。SLP在进行收益评估时仅考虑代码段整体向量化的收益,并没有考虑到向量化收益为负的片段会降低最终整体的向量化收益,从而导致SLP方法无法达到最好的向量化效果。基于此,本文提出了一种基于剪切的SLP向量化方法(Throttling SLP,TSLP),通过寻找最优的向量化子图,去除了向量化收益为负的代码段,从而可以获得更好的向量化效果。通过标准测试程序的实验结果表明,与原来的SLP方法相比,TSLP方法平均能够获得9%的性能提升。