一种精确的有机薄膜晶体管模型参数提取方法研究

提出了一种可以精确获得有机薄膜晶体管(OTFT)的直流电流-电压模型中的参数提取方法。该方法通过对实验获得的输出特性曲线和转移特性曲线进行计算和处理,精确获得OTFT器件模型中的7个参数。实验制备了两种采用不同绝缘栅的基于并五苯的底栅顶接触的OTFT,并对其进行了参数提取。利用提取的参数及直流电流-电压模型对OTFT进行模拟,将模拟结果与实验测试结果相比较发现,模拟得到的输出特性及转移特性与测试结果拟合得很好,验证了本文中参数提取方法的正确性。应用建立的模型及本文中的参数提取方法可以用于OTFT器件的设计与模拟。     

有机薄膜晶体管直流电流-电压模型的研究

通过对有机薄膜晶体管(OTFT)电流-电压特性的研究,建立了一种用于电路模拟的仿真程序(SPICE)的OTFT直流电流-电压模型,所用的参数都可从实验特性曲线中提取。对一种基于并五苯(Pentacene)的底栅顶接触(TC)结构的OTFT的实验曲线进行参数提取,并利用所得的参数与建立的模型进行仿真,得到的输出特性和转移特性曲线与实验结果无论在线性区还是在饱和区都具有较强的一致性,验证了本文所建模型及参数的准确性。建立的模型能够准确描述OTFT的直流特性,可用于有机电路的SPICE仿真。     

GaAs工艺监测研究

介绍了GaAs MMIC(GaAs microwave monolithic integrated circuit)工艺运用监测技术控制工艺过程,实时掌握工艺状况,保证产品的一致性、可重复性和可靠性。针对薄层电阻和接触电阻的阻值以及器件的栅阻和栅长等工艺过程中关键的参数,分别用范德堡结构、开尔文结构和十字桥结构进行监测。采用范德堡结构测得薄层电阻Rs=(π/ln 2)V14/I23,开尔文结构得到接触电阻Rc=V13/I24,十字桥结构可以了解栅阻和栅长。然后通过运用统计过程控制技术对数据进行分析,可以有效改进工艺,提高产品质量。     

InAs/AlSb异质结的Pd/Ti/Pt/Au合金化欧姆接触

为了得到较低的接触电阻, 研究了帽层未掺杂的InAs/AlSb异质结的Pd/Ti/Pt/Au合金化欧姆接触.利用传输线模型 (TLM) 测量了接触电阻Rc.在最佳的快速热退火条件为275℃和20s时, InAs/AlSb异质结的Pd/Ti/Pt/Au接触电阻值为0.128Ω·mm.TEM观察发现经过快速热退火后Pd已经扩散到半导体中有利于高质量欧姆接触的形成.研究表明经过Pd/Ti/Pt/Au合金化欧姆接触后Rc有明显减小, 适用于InAs/AlSb异质结的应用.     

InAs/AlSb异质结的Pd/Ti/Pt/Au合金化欧姆接触（英文）

为了得到较低的接触电阻,研究了帽层未掺杂的InAs/AlSb异质结的Pd/Ti/Pt/Au合金化欧姆接触.利用传输线模型(TLM)测量了接触电阻Rc.在最佳的快速热退火条件为275℃和20s时,InAs/AlSb异质结的Pd/Ti/Pt/Au接触电阻值为0.128Ω·mm.TEM观察发现经过快速热退火后Pd已经扩散到半导体中有利于高质量欧姆接触的形成.研究表明经过Pd/Ti/Pt/Au合金化欧姆接触后Rc有明显减小,适用于InAs/AlSb异质结的应用.     

有机薄膜晶体管(OTFT)的研究进展

有机薄膜晶体管(organic thin film transistor,OTFT)具有工艺简单、成本低及柔韧性良好等优点,成为下一代显示技术的研究焦点.本文综述了有机薄膜晶体管的研究现状和未来的发展趋势,比较了采用不同材料的OTFT器件的性能,总结了影响OTFT性能的两大主要因素,即栅极绝缘层与有机有源层之间的界面特性和有机有源层与源/漏电极之间欧姆接触电阻的大小,并详细综述了改善OTFT性能的最新方法和研究成果.     

基于双结模型非理想太阳能电池伏安特性参数数值分析

提出了一种对于太阳电池光照条件和暗特性条件下对其伏安特性全段进行拟合提取参数的改进方法.对太阳电池J-V曲线进行分段, 提取每段的4个关键参数: 串联电阻(Rs)、并联电阻(Rsh)、品质因子(n)、反向饱和电流密度(J0).这种方法采用了双结电路模型法, 并以CdS/CdTe薄膜电池为例进行了光照下和暗特性分析, 得到了比单结电流模型更多的参数, 并且具有较高的拟合精度(误差<0.7%).     

GaAs MMIC用无源元件的模型

制作了不同结构参数的GaAs MMIC无源元件,包括矩形螺旋电感、MIM电容和薄膜电阻,建立了无源元件的等效电路模型库,采用多项式公式表征无源元件的模型参数和性能参数,便于电路设计的应用.并提取得到MIM电容的单位面积电容值,约为195pF/mm2,NiCr薄膜电阻的方块电阻约为16.1Ω/□.分析结构参数对螺旋电感性能的影响可知,减小线圈面积相关的寄生损耗有助于获得高品质的电感.     

GaAs MMIC用无源元件的模型

制作了不同结构参数的GaAs MMIC无源元件,包括矩形螺旋电感、MIM电容和薄膜电阻,建立了无源元件的等效电路模型库,采用多项式公式表征无源元件的模型参数和性能参数,便于电路设计的应用.并提取得到MIM电容的单位面积电容值,约为195pF/mm2,NiCr薄膜电阻的方块电阻约为16.1Ω/□.分析结构参数对螺旋电感性能的影响可知,减小线圈面积相关的寄生损耗有助于获得高品质的电感.     

一个实用的部分耗尽SOI器件体接触仿真模型

文章描述了PD SOI器件的体接触失效过程,介绍了一种PD SOI器件一级近似体接触电阻计算方法;提出了一种实用的体接触电阻及其版图寄生参数的模型化方法.最后,应用体接触模型,设计了一个应用于0.8 μm PD SOI 128k SRAM的灵敏放大器,给出了仿真结果.     

On Faster I DDQ Measurements

The purpose of this paper is to introduce a new I _DDQ measurement technique based on active successive approximations, called ASA-I _DDQ. This technique has unique features facilitating a speed-up in I _DDQ measurement. Experimental results suggest that a significant speed-up factor (up to 4) can be obtained over the QuiC-Mon technique. Such a speed-up is a key element in the replacement of single-threshold I _DDQ testing since it amplifies the effectiveness of post-processing techniques.     

Performance analysis of 20 nm gate-length In0.2Al0.8N/GaN HEMT with Cu-gate having a remarkable high ION/IOFF ratio

Abstract： We propose a new structure of InxAll-xN/GaN high electron mobility transistor （HEMT） with gate length of 20 nm. The threshold voltage of this HEMT is achieved as -0.472 V. In this device the InA1N barrier layer is intentionally n-doped to boost the ION/IOFF ratio. The InAlN layer acts as donor barrier layer for this HEMT which exhibits an ION = 10-4.3 A and a very low IOFF = 10-14.4 A resulting in an ION/IoFF ratio of 1010.1. We compared our obtained results with the conventional InAlN/GaN HEMT device having undoped barrier and found that the proposed device has almost l0s times better ION/IOFF ratio. Further, the mobility analysis in GaN channel of this proposed HEMT structure along with DC analysis, C-V and conductance characteristics by using small-signal analysis are also presented in this paper. Moreover, the shifts in threshold voltage by DIBL effect and gate leakage current in the proposed HEMT are also discussed. InAlN was chosen as the most preferred barrier layer as a replacement of AlGaN for its excellent thermal conductivity and very good scalability.     

Monitoring Power Dissipation for Fault Detection

In this paper, we suggest that the dynamic power dissipation of acircuit can be used for fault detection. Even those faults which do notaffect static power dissipation can be detected by monitoring dynamic powerdissipation. We discuss how stuck-at, stuck-open, and redundant faults maybe detected by monitoring dynamic power dissipation. In many cases, theFourier spectra of the supply currents in the good and faulty circuits willalso be very different. Further, specific tests can be applied so as toimprove fault coverage. Power monitoring is verified using simulation, andalso experimentally, for example circuits.     

Defect Diagnosis Using a Current Ratio Based Quiescent Signal Analysis Model for Commercial Power Grids

Quiescent Signal Analysis (QSA) is a novel electrical-test-based diagnostic technique that uses I _DDQ measurements made at multiple chip supply pads as a means of locating shorting defects in the layout. The use of multiple supply pads reduces the adverse effects of leakage current by scaling the total leakage current over multiple measurements. In previous work, a resistance model for QSA was developed and demonstrated on a small circuit. In this paper, the weaknesses of the original QSA model are identified, in the context of a production power grid (PPG) and probe card model, and a new model is described. The new QSA algorithm is developed from the analysis of I _DDQ contour plots. A family of hyperbola curves is shown to be a good fit to the contour curves. The parameters to the hyperbola equations are derived with the help of inserted calibration transistors. Simulation experiments are used to demonstrate the prediction accuracy of the method on a PPG.     

LEAP: An Accurate Defect-Free IDDQ Estimator

The quiescent current (I _DDQ) consumed by a CMOS IC is a good indicator of the presence of a large class of defects. However, the effectiveness of I _DDQ testing requires appropriate discriminability of defective and defect-free currents, and hence it becomes necessary to estimate the currents involved in order to design the I _DDQ test. In this work, we present a method to estimate accurately the non-defective I _DDQ consumption based on a hierarchical approach at electrical (cell) and logic (circuit) levels. This accurate estimator is used in conjunction with an ATPG (Automatic Test Pattern Generation) to obtain vectors having low/high defect-free I _DDQ currents.     

IDDQ Testing of Submicron CMOS—by Cooling?

The usability of I _DDQ testing is limited by the subthreshold currents of the low-V _T, submicron MOS transistors in the low bias voltage circuits. The paper addresses the cooling of the chip in order to overcome this problem. Experimental results concerning the effect of cooling on the threshold voltage and subthreshold current are presented in the range of –75...25 Centigrade. The subthreshold currents decrease by a factor of about 100–1000 by cooling-down the chip to –75 Centigrade.     

Algorithms for I DDQ measurement based diagnosis of bridging faults

In the absence of information about the layout one is left with no alternative but to consider all bridging faults. An algorithm for diagnosis of a subset of such faults, viz. single two line bridging faults in static CMOS combinational circuits is presented. This algorithm uses results from I _DDQ measurement based testing.Unlike known diagnosis algorithms, this algorithm does not use fault dictionaries, it uses only logic simulation and uses no fault simulation. It also uses SOPS, a novel representation of subsets of two-line bridging faults resulting in an efficient algorithm.In spite of the large number of faults that we consider, our experimental results point to the computational feasibility of I _DDQ Measurement based diagnosis of single two line bridging faults. It also shows the effectiveness of reducing the set of possible faults using I _DDQ measurements.A preliminary version of this work was presented at the 29th ACM/IEEE Design Automation Conference, 1992.Research Partially Supported by NSF Grant No. MIP-9102509.This work was performed when the author was with the Dept. of Computer Science, State University of New York at Buffalo.     

Quietest: A methodology for selecting I DDQ test vectors

Even high stuck-at fault coverage manufacturing test programs cannot assure high quality for CMOS VLSI circuits. Measurement of quiescent power supply current (I _DDQ ) is a means of improving quality and reliability by detecting many defects that do not have appropriate representation in the stuck-at fault model. Since each I _DDQ measurement takes significant time, a hierarchical fault analysis methodology is proposed for selecting a small subset of production test vectors for I _DDQ measurements. A software system QUIETEST has been developed on the basis of this methodology. For two VLSI circuits QUIETEST selected less than 1% of production test vectors for covering all modeled faults that would have been covered by I _DDQ measurement for all of the vectors. The fault models include leakage faults and weak faults for representing defects such as gate oxide shorts and certain opens.     

Diagnosis of leakage faults with I DDQ

Recently there has been renewed interest in fault detection in static CMOS circuits through I _DDQ monitoring. This work shows that, in addition to fault detection, accurate fault diagnosis may be performed using a combination of current and voltage observations. The proposed system combines a simple single fault model for test generation with a more realistic multiple defect model for diagnosis, and as a result requires only minor modifications to existing stuck-at fault ATPG software. The associated hardware is sufficiently simple that on-board implementation is possible. Experimental results demonstrate the effectiveness of the method on a standard-cell ASIC.