Architecting high-performance energy-efficient soft error resilient cache under 3D integration technology

Radiation-induced soft error has become an emerging reliability threat to high performance microprocessor design. As the size of on chip cache memory steadily increased for the past decades, resilient techniques against soft errors in cache are becoming increasingly important for processor reliability. However, conventional soft error resilient techniques have significantly increased the access latency and energy consumption in cache memory, thereby resulting in undesirable performance and energy efficiency degradation. The emerging 3D integration technology provides an attractive advantage, as the 3D microarchitecture exhibits heterogeneous soft error resilient characteristics due to the shielding effect of die stacking. Moreover, the 3D shielding effect can offer several inner dies that are inherently invulnerable to soft error, as they are implicitly protected by the outer dies. To exploit the invulnerability benefit, we propose a soft error resilient 3D cache architecture, in which data blocks on the soft error invulnerable dies have no protection against soft error, therefore, access to the data block on the soft error invulnerable die incurs a considerably reduced access latency and energy. Furthermore, we propose to maximize the access on the soft error invulnerable dies by dynamically moving data blocks among different dies, thereby achieving further performance and energy efficiency improvement. Simulation results show that the proposed 3D cache architecture can reduce the power consumption by up to 65% for the L1 instruction cache, 60% for the L1 data cache and 20% for the L2 cache, respectively. In general, the overall IPC performance can be improved by 5% on average.     

ReStore: Symptom-Based Soft Error Detection in Microprocessors

Device scaling and large-scale integration have led to growing concerns about soft errors in microprocessors. To date, in all but the most demanding applications, implementing parity and ECC for caches and other large, regular SRAM structures have been sufficient to stem the growing soft error tide. This will not be the case for long and questions remain as to the best way to detect and recover from soft errors in the remainder of the processor—in particular, the less structured execution core. In this work, we propose the ReStore architecture, which leverages existing performance enhancing checkpointing hardware to recover from soft error events in a low cost fashion. Error detection in the ReStore architecture is novel: symptoms that hint at the presence of soft errors trigger restoration of a previous checkpoint. Example symptoms include exceptions, control flow misspeculations, and cache or translation look-aside buffer misses. Compared to conventional soft error detection via full replication, the ReStore framework incurs little overhead, but sacrifices some amount of error coverage. These attributes make it an ideal means to provide very cost effective error coverage for processor applications that can tolerate a nonzero, but small, soft error failure rate. Our evaluation of an example ReStore implementation exhibits a 2x increase in MTBF (mean time between failures) over a standard pipeline with minimal hardware and performance overheads. The MTBF increases by 20x if ReStore is coupled with protection for certain particularly vulnerable pipeline structures.     

龙芯1号处理器的故障注入方法与软错误敏感性分析

在纳米级制造工艺下以及在航天等特殊应用场合中，可靠性将是处理器设计中的一个重要考虑因素．以龙芯1号处理器为研究对象，探讨了处理器可靠性设计中的故障注入方法，并提出了一种同时运行两个处理器RTL模型的故障注入与分析方法，可以实现连续快速的处理器仿真故障注入．在此基础上，进一步分析了龙芯1号处理器的软错误敏感性，通过快速注入大约30万个软错误，保证了分析结果具有较好的统计意义，可以有效指导后续的容错与可靠性设计．     

Reducing Soft Errors through Operand Width Aware Policies

Soft errors are an important challenge in contemporary microprocessors. Particle hits on the components of a processor are expected to create an increasing number of transient errors with each new microprocessor generation. In this paper, we propose simple mechanisms that effectively reduce the vulnerability to soft errors in a processor. Our designs are generally motivated by the fact that many of the produced and consumed values in the processors are narrow and their upper order bits are meaningless. Soft errors caused by any particle strike to these higher order bits can be avoided by simply identifying these narrow values. Alternatively, soft errors can be detected or corrected on the narrow values by replicating the vulnerable portion of the value inside the storage space provided for the upper order bits of these operands. As a faster but less fault tolerant alternative to ECC and parity, we offer a variety of schemes that make use of narrow values and analyze their efficiency in reducing soft error vulnerability of different data-holding components of a processor. On average, techniques that make use of the narrowness of the values can provide 49 percent error detection, 45 percent error correction, or 27 percent error avoidance coverage for single bit upsets in the first level data cache across all Spec2K. In other structures such as the immediate field of the issue queue, an average error detection rate of 64 percent is achieved.     

An experimental study of soft errors in microprocessors

The issue of soft errors is an important emerging concern in the design and implementation of future microprocessors. The authors examine the impact of soft errors on two different microarchitectures: a DLX processor for embedded applications and a high-performance alpha processor. The results contrast impact of soft errors on combinational and sequential logic, identify the most vulnerable units, and assess soft error impact on the application.     

Exploiting Narrow Values for Soft Error Tolerance

Soft errors are an important challenge in contemporary microprocessors. Particle hits on the components of a processor are expected to create an increasing number of transient errors with each new microprocessor generation. In this paper we propose simple mechanisms that effectively reduce the vulnerability to soft errors In a processor. Our designs are generally motivated by the fact that many of the produced and consumed values in the processors are narrow and their upper order bits are meaningless. Soft errors canted by any particle strike to these higher order bits can be avoided by simply identifying these narrow values. Alternatively soft errors can be detected or corrected on the narrow values by replicating the vulnerable portion of the value inside the storage space provided for the upper order bits of these operands. We offer a variety of schemes that make use of narrow values and analyze their efficiency in reducing soft error vulnerability of level-1 data cache of the processor     

Tolerating Radiation-Induced Transient Faults in Modern Processors

As MOS device sizes continue shrinking, lower charges, for example those charges carried by single ionizing particles of naturally occurring radiation, are sufficient to upset the functioning of complex modern microprocessors. In order to handle these inevitable errors, designs should include fault-tolerant features so that the processors can continue to correctly perform despite the occurrence of errors. The main goal of this work is to develop architecture mechanisms to protect processors against the effect of such radiation-induced transient faults. It should first be noted that, from a program execution perspective, many faults manifest themselves as control flow errors that cause processors to violate the correct sequencing of instructions. We present here at first a basic compile-time signature assignment algorithm and describe a novel approach to improve the fault detection coverage of the basic algorithm. Moreover, to allow the processor to efficiently check the run-time sequence and detect control flow errors, we introduce an on-chip assigned-signature checker which is capable of executing three additional instructions (SIC, SIJ, SIJC). Second, since the very concept of simultaneous multi-threading (SMT) provides the necessary redundancy, some proposals have been made to run two copies of the same thread on top of SMT platforms in order to detect and correct soft errors. This allows, upon detection of an error, the rolling back of the processor state to a known safe point, and then a retry of the instructions, thereby effecting a completely error-free execution. This paper has focused on two crucial implementation issues introduced by this scheme: (1) the design trade-off between the fault detection coverage versus design costs; (2) the possible occurrence of deadlock situations.     

基于VPM和随机激励的处理器核仿真建模

为提高处理器核仿真模型的效率,提出基于SimpleScalar架构对龙芯1号处理器进行虚拟处理器模型行为建模,IPC平均误差为2.3%,速度达到每秒1 000 000条指令。基于可控随机事件机制实现的总线功能模型可以为片上系统(SoC)设计提供激励主动生成方案和片上互连验证功能。实验结果证明,该方法对处理器IP仿真建模具有普适意义,能够被无缝融入SoC流程中。     

Accurate and Simplified Prediction of AVF for Delay and Energy Efficient Cache Design

With continuous technology scaling,on-chip structures are becoming more and more susceptible to soft errors.Architectural vulnerability factor (AVF) has been introduced to quantify the architectural vulnerability of on-chip structures to soft errors.Recent studies have found that designing soft error protection techniques with the awareness of AVF is greatly helpful to achieve a tradeoff between performance and reliability for several structures (i.e.,issue queue,reorder buffer).Cache is one of the most susceptible components to soft errors and is commonly protected with error correcting codes (ECC).However,protecting caches closer to the processor (i.e.,L1 data cache (L1D)) using ECC could result in high overhead.Protecting caches without accurate knowledge of the vulnerability characteristics may lead to over-protection.Therefore,designing AVF-aware ECC is attractive for designers to balance among performance,power and reliability for cache,especially at early design stage.In this paper,we improve the methodology of cache AVF computation and develop a new AVF estimation framework,soft error reliability analysis based on SimpleScalar.Then we characterize dynamic vulnerability behavior of L1D and detect the correlations between L1D AVF and various performance metrics.We propose to employ Bayesian additive regression trees to accurately model the variation of L1D AVF and to quantitatively explain the important effects of several key performance metrics on L1D AVF.Then,we employ bump hunting technique to reduce the complexity of L1D AVF prediction and extract some simple selecting rules based on several key performance metrics,thus enabling a simplified and fast estimation of L1D AVF.Based on the simplified and fast estimation of L1D AVF,intervals of high L1D AVF can be identified online,enabling us to develop the AVF-aware ECC technique to reduce the overhead of ECC.Experimental results show that compared with traditional ECC technique which provides complete ECC protection throughout the entire lifetime of a program,AVF-aware ECC technique reduces the L1D access latency by 35% and saves power consumption by 14% for SPEC2K benchmarks averagely.     

片上多核处理器容软错误执行模型

随着工艺的进步,微处理器将面临越来越严重的软错误威胁.文中提出了两种片上多核处理器容软错误执行模型:双核冗余执行模型DCR和三核冗余执行模型TCR.DCR在两个冗余的内核上以一定的时间间距运行两份相同的线程,store指令只有在进行了结果比较以后才能提交.每个内核增加了硬件实现的现场保存与恢复机制,以实现对软错误的恢复.文中选择的现场保存点有利于隐藏现场保存带来的时间开销,并且采用了特殊的机制保证恢复执行和原始执行过程中load数据的一致性.TCR执行模型通过在3个不同的内核上运行相同的线程实现对软错误的屏蔽.在检测到软错误以后,TCR可以进行动态重构,屏蔽被软错误破坏的内核.实验结果表明,与传统的软错误恢复执行模型CRTR相比,DCR和TCR对核间通信带宽的需求分别降低了57.5%和54.2%.在检测到软错误的情况下,DCR的恢复执行带来5.2%的性能开销,而TCR的重构带来的性能开销为1.3%.错误注入实验表明,DCR能够恢复99.69%的软错误,而TCR实现了对SEU(Single Event Upset)型故障的全面屏蔽.     

基于最小重构误差的优化局部聚合描述符向量图像检索算法

针对局部聚合描述符向量(VLAD)模型中对特征软量化时权重系数的取值不确定性和特征量化误差较大问题,提出一种具有最小重构误差的权重系数分配算法。该算法以最小化重构误差为标准,将具有最小化重构误差的稀疏编码的编码系数作为软量化VLAD的权重系数。数据库的图像检索测试结果表明,该算法相比主流的VLAD特征编码算法所得图像检索精度可提高10%左右,且有更小的特征重构误差。     

LSE：一种处理器体系结构软件仿真器开发工具

在现代处理器体系结构设计中,利用软件仿真技术对设计结果进行验证是最重要的方面之一.然而,处理器体系结构仿真器的开发是一个非常困难的过程.主要的困难表现在三个方面:第一,目前用于处理器体系结构仿真器开发的编程语言如C或C 语言都是串行执行的语言,而处理器的各部件是可以并行运行的,使用串行编程语言编程来模拟并行执行的部件需要长时间的、仔细的程序功能与部件功能的匹配工作,并且容易出错;第二,使用串行程序来模拟并行部件的运行,模拟速度很低,并且仿真速度低是处理器体系结构软件仿真器开发领域的瓶颈问题;最后,仿真器仿真结果的可信度低也是一个关键问题.本文首先介绍了一种新的处理器体系结构软件仿真器开发工具,然后深入分析了该开发工具的优点和缺点,最后对该仿真器开发环境提出了改进方案.     

基于指令行为的Cache可靠性评估研究

软错误由高能粒子撞击所产生,对处理器的可靠性产生很大的损害.随着处理器设计目标转向低功耗、高性能和低供电电压,软错误的发生日益频繁,处理器的可靠性研究也随之受到越来越多的关注.针对传统的基于注错仿真的可靠性评估方法效率低的缺陷,提出了一套系统的cache可靠性评估方法,以可靠性指标之一--体系结构易受损因子(architectural vulnerability factor,AVF))--为研究对象,一方面,基于指令行为分析应用程序运行过程中对最终结果不产生影响的指令,从而确定对cache的AVF产生作用的指令;另一方面,根据cache的存储类型、所采取的写策略,结合cache中数据/指令阵列和地址标识阵列的特点,对cache上的各种相邻操作组合对AVF的影响进行了研究,从而完成AVF评估所需的信息分析.实验部分对PISA体系结构指令cache中的指令阵列进行了AVF评估,说明了该方法的有效性.     

Hybrid functional- and instruction-level power modeling for embedded and heterogeneous processor architectures

In this contribution the concept of functional- level power analysis (FLPA) for power estimation of programmable processors is extended in order to model embedded as well as heterogeneous processor architectures featuring different embedded processor cores. The basic FLPA approach is based on the separation of the processor architecture into functional blocks like, e.g. processing unit, clock network, internal memory, etc. The power consumption of these blocks is described by parameterized arithmetic models. By application of a parser based automated analysis of assembler codes the input parameters of the arithmetic functions like e.g. the achieved degree of parallelism or the kind and number of memory accesses can be computed. For modeling an embedded general purpose processor (here, an ARM940T) the basic FLPA modeling concept had to be extended to a so-called hybrid functional-level and instruction-level (FLPA/ILPA) model in order to achieve a good modeling accuracy. In order to show the applicability of this approach even a heterogeneous processor architecture (OMAP5912) featuring an ARM926EJ-S core and a C55x DSP core has been modeled using the hybrid FLPA/ILPA technique described before. The approach is exemplarily demonstrated and evaluated applying a variety of basic digital signal processing tasks ranging from basic filters to complete audio decoders or classical benchmark suits. Estimated power figures for the inspected tasks are compared to physically measured values for both inspected processor architectures. A resulting maximum estimation error of 9% for the ARM940T and less than 4% for the OMAP5912 is achieved.     

A strictly convergent real-time solution for inverse kinematics of robot manipulators

Inverse Kinematics has been recognized as an important problem in robotics applications. A robot independent solution can only be obtained through numerical methods, but most solutions which use this approach have problems with convergence especially near singularity points. This article develops a strictly convergent algorithm and a special-purpose Inverse Kinematics Processor (IKP) to obtain the solution in real time. While the algorithm is based on open-loop integration of rates, the absolute position deviation is used as a criterion to control the iteration, and a feedback mechanism has been especially designed to eliminate problems with long-term drift or with initial errors in the solution. The architecture of the IKP is based on a high-speed floating-point arithmetic processor and is designed to perform the common matrix-vector operations efficiently with a minimum processor cycle time. The algorithm has been simulated on the proposed architecture, and the results show its robustness and real-time capability. For a six degree-of-freedom robot manipulator (for which no closed-form solution exist), the Inverse Kinematics solution may be obtained at an approximate 2 khz rate with an error which is within standard repeatability limits.     

基于混合纠错码的可容错性高速缓存研究

针对低电压下,Cache硬错误和软错误概率提高导致Cache不能正常工作的问题,提出了一种基于混合纠错码的Cache结构。该结构利用脏数据正确性必须由处理器中Cache保证而干净数据可由片外恢复的数据特征,将Cache分成多比特纠错码和单比特纠错码保护的两个区域。通过采用新的Cache替换策略,使得脏数据总处于多比特纠错码保护区域,保证其得到较强保护,从而保证Cache在低电压下的可靠性运行。基于EEMBC测试基准的实验结果表明,该设计可以在590mv电压下正常运行,与该领域最新研究 VS-ECC相比,降低了23.6%的纠错码存储信息量,性能提高5.9%。     

面向崩溃预测的寄存器软错误故障传播分析

故障注入是研究软错误故障传播的传统手段,但随着程序复杂性不断增加,采用故障注入对大量软错误的故障传播进行研究将花费巨大的时间成本。提出一种基于程序动态指令进行分析和建模从而快速获取软错误结果的方法。将程序转化为动态指令序列,通过体系结构正确执行分析将所有可能的软错误划分为对程序运行结果有影响和没有影响两部分;基于动态依赖图建立软错误故障传播分析模型,并建立判断程序崩溃的标准,进而提出一个算法对任意制定的能够影响程序运行结果的软错误进行故障传播分析并重点预测程序崩溃的发生。实验显示,预测的漏报率和分析单个软错误的平均用时明显低于现有方法。     

Soft error susceptibility analysis methodology of HLS designs in SRAM-based FPGAs

SRAM-based FPGAs are attractive to critical applications due to their reconfiguration capability, which allows the design to be adapted on the field under different upset rate environments. High level Synthesis (HLS) is a powerful method to explore different design architectures in FPGAs. In this paper, the HLS tool from Xilinx is used to generate different design architectures and then analyze the probability of errors in those architectures. Two different case studies scenarios are investigated. First, it is evaluated the influence of control flow and pipeline architectures combined with the use of specialized DSP blocks in the FPGA. The number of errors classified as silent data corruption and timeout according to the architectures and DSP blocks usage is analyzed. Moreover, more possibilities of HLS designs are explored such as data organization, aggressive pipeline insertion and the implementation of the algorithm in a soft processor like the Microblaze from Xilinx. These architectures are strongly optimized in performance and the least susceptible design under soft errors is investigated. All case-study designs are evaluated in a 28 nm SRAM-based FPGA under fault injection. The dynamic cross section, soft error rate and mean work between failures are calculated based on the experimental results. The proposed characterization method can be used to guide designers to select better architectures concerning the susceptibility to upsets and performance efficiency.     

基于模糊控制与预测控制切换的翼伞系统航迹跟踪控制

以翼伞系统的六自由度模型为基础,针对翼伞系统的平面航迹跟踪问题,对已有的预测控制器进行改进,提出模糊控制和广义预测控制相互切换的控制模式．利用横向轨迹误差法,在翼伞偏航角误差较大的情况下,采用模糊控制,直至偏航角误差达到设定的较小范围内,切换为广义预测控制,对翼伞航迹进行精确的制导,在一定程度上减少了处理器的运算量．采用真实的翼伞参数建立仿真模型,结果验证了这一控制方法的有效性．     

基于SOPC的SCSI应用系统设计方法的研究

在分析了SCSI应用系统结构和常规设计方法的基础上，提出了一种基于可编程片上系统和处理器软核技术的SCSI应用系统的设计方案，其中应用系统控制核心选用了基于NIOS软核的微处理器，将SCSI控制单元的外部主机处理器，DMA数据通道控制和数据缓存控制逻辑等集成在1片FPGA上实现，在能充分利用逻辑器件资源的同时，使得设计更紧凑、灵活、高速和可靠，