用FPGA实现16位格雷码译码和工程量显示

采用FPGA实现绝对式光电编码器格雷码输出的译码和工程量显示电路。设计包括FPGA的硬件电路设计,电路功能的VHDL语言设计和实现,以及采用JTAG边界扫描测试标准实现电路的在系统编程(ISP)等。     

基于FPGA的LTE-TDD接收系统设计与实现

介绍了一种基于FPGA的LTE-TDD接收系统设计与实现,采用中频带通采样技术实现LTE-TDD信号接收,可进一步提升其系统带宽.给出了基于FPGA的LTE-TDD接收系统具体设计方案,并对各部分主要电路设计进行了详细阐述,包括信号调理电路、A/D转换器电路、FPGA电路以及电源电路设计.该系统由于采用了FPGA,因此...     

基于比特平面的快速中值滤波器设计与实现

提出基于比特平面的快速中值滤波算法硬件实现结构和核心处理电路,在减少了中值滤波电路面积的情况下,显著提高了处理速度.提出的比特平面算法硬件实现结构的面积与滤波数据长度和量化比特教成近似线性关系,适于各种滤波窗口大小和数据精度的中值滤波;算法硬件实现结构规则,特别适于用FPGA实现.     

以FPGA为核心的液晶显示电路设计与实现

介绍了采用大规模可编程逻辑器件(FPGA)设计与实现液晶显示电路的一种新的方法。设计了以FPGA为核心的液晶显示、控制硬件电路和基于硬件描述语言(VHDL)的各功能模块,相应地设计了外围驱动电路;通过对驱动电路的分析,设计了时钟模块、串行接口电路、内部RAM块、读写电路以及时序产生电路,并将多个模块集成在一片FPGA芯片上,实现了80×64点阵液晶屏的实时显示。通过扩展外部的行、列驱动器和利用FPGA的快速定制性,可方便地实现更多像素点的液晶显示,增强了系统的灵活性。     

基于FPGA的数据采集电路设计

数据采集技术被广泛应用于电子、通信、医疗器械、工业仪表等行业中。文中介绍了一种基于FPGA的数据采集电路设计,该电路采用了ADC＋FPGA＋USB的实现方案,在对电路总体设计进行阐述的基础上,给出了各个主要电路的设计方法。该数据采集电路由于采用了FPGA作为数据处理平台,其可编程特点使得该系统具有较强的通用性和实用价值。     

图像边缘检测系统的硬件设计

介绍了一种视频检测系统中图像边缘检测子系统的设计方案及其实现过程。选择Sobe!算子作为设计系统的核心算子。该系统采用Ahera公司的FPGA（现场可编程门阵列）芯片作为中央处理器,由帧数据接收模块、像素值串入并出模块、像素窗口刷新模块、数据处理模块及相关配置电路组成。像素窗口刷新模块本质为一个移位寄存器,用于实现像素处理窗口的更新,并将更新后的数据送入数据处理模块实现Sobel算法和整个图像边缘检测的过程。系统在QuartusII软件平台下开发,通过仿真证明符合设计要求,并被成功下载到Cyclone系列FPGA中。本系统还可应用在需要对图像进行高速处理的场合。     

FPGA电路动态老化技术研究

近年来,随着FPGA电路在军工和航天领域的广泛应用,用户对FPGA电路的可靠性要求也越来越高。在集成电路的可靠性评估试验中,动态老化试验是最重要的试验之一,FPGA动态老化技术的实现可以提高FPGA电路的可靠性。文章通过研究FPGA电路内部结构和功能模块,讨论FPGA电路加载配置过程的原理和流程,通过对动态老化和静态老化的对比试验和结果分析,研究出FPGA电路动态老化试验方法,并在工程实践中得到了成功实现和应用。     

FM-DCSK混沌通信系统的原型设计与研究

文中设计了一个基于调频差分混沌键控通信系统的原型,并实现了部分关键电路。系统发射部分由Lorenz混沌电路和调频电路产生混沌调频载波信号,经采样后在FPGA中实现差分延时和调制;接收部分基于非相干相关法,位同步模块采用相关值与能量比值作为定时测度,通过设置门限和滑动搜索窗口寻找初始同步,而后引入数字锁相环进行相关峰值跟踪和位同步调整。建模验证结果表明,系统非相干解调的误码率指标接近理论分析值,仅相差0.2 dB。     

基于FPGA的OLED真彩色显示的实现

利用FPGA控制模块,设计了OLED真彩色动态图像驱动控制电路。介绍采用FPGA实现OLED外围控制电路和256级灰度的方法,并分析电路中模块的作用及整个电路的工作过程。电路系统采用基于Altera公司的FPGA技术进行设计,以Verilog HDL为描述语言,Modelsim仿真结果表明,该方案能够实现预定目标,实现480×RGB×640 彩色OLED 屏256 级灰度显示。     

基于FPGA的任意波形发生器的设计与实现

提出了一种基于FPGA（现场可编程门阵列）采用DDS（直接数字频率合成器）技术的任意波形发生器设计方案。该方案的硬件电路以FPGA为核心器件,辅以D／A转换器、程控放大和人机接口电路构成。其中FPGA内部控制电路采用8051单片机软核为核心进行设计,信号合成电路采用VHDL语言设计数控振荡器实现,低通滤波器为采用窗函数法设计的16阶线性FIR数字滤波器。     

10Gbit/s甚短距离并行光传输模块与实验系统

介绍符合OIF-VSR4-03.0规范的10Gbit/s甚短距离(VSR)实验系统研究.该系统由16×622Mbit/s到4×2.488Gbit/s转换集成电路、自制12通道850nm垂直腔面发射激光器(VCSEL)并行光发射模块和商用12通道并行接收光模块构成.用一片FPGA实现转换芯片的全部功能,采用基于二分查找法的SDH STM-64/OC192 并行帧对齐及同步算法,大大提高了转换芯片的工作速度和节省了逻辑资源,自制12通道VCSEL并行发射模块工作速率达到12×2.488Gbit/s的设计指标.在SDH STM-64/OC192 10Gbit/s测试仪点到点的传输系统测试中,采用5米的12芯400MHz·km 62.5μm多模带状光纤互联,系统误码率低于1×10^-14.     

FIR filter optimization using bit-edge equalization in high-speed backplane data transmission

A unique bit-edge equalization (BEE) method for mitigating intersymbol interference (ISI) in high-speed backplane applications is presented. Using a least-mean-square (LMS) adaptive algorithm as a receiver (RX) error convergence engine, the proposed BEE method aims to optimize the bit-edge amplitudes by equalizing only the edges of data bits with an adjustment of the sampling points where the error information is collected. This adjustment of sampling points in turn changes the error information and affects filter coefficients for pulse amplitude modulation. As a result, the channel's far-end 3-level bit-edge eye diagrams can be optimized. This proposed BEE method employs transmitter (TX) pre-coding in conjunction with TX pre-emphasis using a symbol-spaced FIR (SSF) filter. In this work, a detailed analytical comparison of the proposed BEE transceiver architecture with the conventional NRZ bit-centre equalization (BCE) and duobinary transceiver architectures is presented. The simulation results demonstrate that at 10+ Gbps data rates, the proposed BEE is the most effective method for mitigating ISI in relatively high-loss channels.     

Design of 4.25 Gbps Small Form-factor Pluggable(SFP) Transceiver

Compact, hot-pluggable, and data-agnostic, SFP modules bring up to 4.25 Gbps to a flexible new form factor. The SFP transceiver which is the core device of optical communication is always the research focus in the field of optical communication for both telecommunication and data communication applications. The working principles of SFP including the transmitter components, the receiver components and the microcontroller are discussed in detail. The basic theory of high-speed signal and the concept of high - speed circuit, high-speed board design techniques are presented. A new design of high performance, cost effective SFP transceiver and PCB layout are also presented. The performance of the transceiver is analyzed and the characteristics of the sample are coincident with the expected ones. The status of the transceiver can be monitored and controlled by I2C bus through the interface in real time. This transceiver can meet the requirement of SFF-8472.     

10Gbit／sX4小型可插拔并行光收发模块的研制

研制了一款基于系统级封装技术的低成本、收发一体和可带电热插拔的4通道小型可插拔（QSFP）光模块,采用850nm垂直腔面发射激光器（VCSEL）阵列及其驱动器作为发射端,光电探测器（PD）阵列及其跨阻放大器（TIA）作为接收端,通过光路无源对准,实现了低成本光互连。高速度、高密度封装下的瞬态同步开关噪声、芯片间电磁干扰...     

Low-power LVDS I/O interface for above 2Gb/s-per-pin operation

Low Voltage Differential Signaling (LVDS) has become a popular choice for high-speed serial links to conquer the bandwidth bottleneck of intra-chip data transmission. This paper presents the design and the implementation of LVDS Input/Output (I/O) interface circuits in a standard 0.18 μm CMOS technology using thick gate oxide devices (3.3 V), fully compatible with LVDS standard. In the proposed transmitter, a novel Common-Mode FeedBack (CMFB)circuit is utilized to keep the common-mode output voltage stable ...     

A Gigabit Link CMOS Analog Interface for High Performance Signaling

In this brief, design of a gigabit link CMOS analog interface composed of a transmitter, a receiver, and clocking circuits is addressed with focus on high-performance signaling in terms of interference and jitter. The low-cost, low-power interface is targeted at parallel link applications. The transmitter adopts one-tap preemphasis to mitigate the intersymbol interference (ISI) problem. The receiver samples two adjacent bits and stores the difference of them to a capacitor, so it is more immune to timing uncertainties caused by nonideal sampling clocks and it is dependent only on the direction or difference of two consecutive bits, not on the absolute values of them. With these circuits, robust clocking circuits to multiplex and demultiplex the data on the transmit and receive side, respectively, are designed. Pseudo-differential-type delay elements are used in the oscillator and delay line to enable high power supply rejection ratio and low jitter. The delay locked loop (DLL) is designed to prevent harmonic locking. The transceiver performance is tested at 1 Gbps and 2 Gbps for double and quadruple interleaving, respectively. The maximum operating speed is about 1.7 Gbps for double interleaving and about 3 Gbps for the quadruple-interleaving receiver under a 3.3 V, 0.35 μm CMOS process. Sungkyung Park Large Scale SoC Research Department, Electronics and Telecommunications Research Institute(ETRI), 161 Gajeong-dong, Yuseong-gu, Daejeon 305–350, Korea (fitzgerald1971@yahoo.com) Sungkyung Park received B.S. (with highest honors) and M.S. degrees from Seoul National University, Korea, in 1995 and 1997, respectively. He received a Ph.D. degree in CMOS IC design from Seoul National University, Korea, in 2002. During the military service, from 2002 to Sep. 2004, he was with the Telecommunication Network, Samsung Electronics, Inc., Korea, as a Senior Engineer, where he was engaged in developing cdma 2000 system-level simulators. From Oct. 2004 until now, he has been with the Large Scale SoC Research Department, Electronics and Telecommunications Research Institute (ETRI), Korea, as a Senior Researcher. His research interests cover high-speed analog and mixed-mode CMOS IC design including RF CMOS IC design, data converter design, and issues in wireless/wireline communication SoC/NoC.     

40 Gbit/s多路并行光收发模块的研制

基于VCSEL激光器阵列和PIN探测器阵列,设计和制作了40Gbit/s甚短距离的4通道发射4通道接收并行光收发模块.通过高速电路信号仿真设计,解决了信号完整性、串扰和电磁兼容等问题;通过键合金丝长度设计增加了通道带宽.光模块单通道传输速率可达到5 Gbit/s,8通道并行总传输速率达到40Gbit/s,实现了并行光收发模块高速率、高密度、高可靠性以及小体积设计,为甚短距离高速数据处理和传输提供了高可靠的多路数据链接.     

A Low‐Crosstalk Design of 1.25 Gbps Optical Triplexer Module for FTTH Systems

In this paper, we analyzed and measured the electrical crosstalk characteristics of a 1.25 Gbps triplexer module for Ethernet passive optical networks to realize fiber‐to‐the‐home services. Electrical crosstalk characteristic of the 1.25 Gbps optical triplexer module on a resistive silicon substrate should be more serious than on a dielectric substrate. Consequently, using the finite element method, we analyze the electrical crosstalk phenomena and propose a silicon substrate structure with a dummy ground line that is the simplest low‐crosstalk layout configuration in the 1.25 Gbps optical triplexer module. The triplexer module consists of a laser diode as a transmitter, a digital photodetector as a digital data receiver, and an analog photodetector as a cable television signal receiver. According to IEEE 802.3ah and ITU‐T G.983.3, the digital receiver and analog receiver sensitivities have to meet ‐24 dBm at BER=10^?12 and ‐7.7 dBm at 44 dB SNR. The electrical crosstalk levels have to maintain less than ‐86 dB from DC to 3 GHz. From analysis and measurement results, the proposed silicon substrate structure that contains the dummy line with 100 μm space from the signal lines and 4 mm separations among the devices satisfies the electrical crosstalk level compared to a simple structure. This proposed structure can be easily implemented with design convenience and greatly reduce the silicon substrate size by about 50 %.     

Transceiver for Human Body Communication Using Frequency Selective Digital Transmission

This paper presents a transceiver module for human body communications whereby a spread signal with a group of 64 Walsh codes is directly transferred through a human body at a chip rate of 32 Mcps. Frequency selective digital transmission moves the signal spectrum over 5 MHz without continuous frequency modulation and increases the immunity to induced interference by the processing gain. A simple receiver structure with no additional analog circuitry for the transmitter has been developed and has a sensitivity of 250 µV_pp. The high sensitivity of the receiver makes it possible to communicate between mobile devices using a human body as the transmission medium. It enables half‐duplex communication of 2 Mbps within an operating range of up to 170 cm between the ultra‐mobile PCs held between fingertips of each hand with a packet error rate of lower than 10^?6. The transceiver module consumes 59 mA with a 3.3 V power supply.     

A 6 Gbps/pin Low‐Power Half‐Duplex Active Cross‐Coupled LVDS Transceiver with Switched Termination

A novel linear switched termination active cross‐coupled low‐voltage differential signaling (LVDS) transceiver operating at 1.5 GHz clock frequency is presented. On the transmitter side, an active cross‐coupled linear output driver and a switched termination scheme are applied to achieve high speed with low current. On the receiver side, a shared preamplifier scheme is employed to reduce power consumption. The proposed LVDS transceiver implemented in an 80 nm CMOS process is successfully demonstrated to provide a data rate of 6 Gbps/pin, an output data window of 147 ps peak‐to‐peak, and a data swing of 196 mV. The power consumption is measured to be 4.2 mW/pin at 1.2 V.