一种用于FPGA的可配置存储器设计

设计了一种用于FPGA中的同步、双端口、容量为4kbit、可配置的存储器模块(Block RAM,BRAM)。BRAM以阵列形式内嵌在FPGA内部,是FPGA的主要模块之一。该BRAM可实现1、2、4、8、16bit 5种不同的数据位宽,且具有数据初始化及回读验证的功能。本文分别对BRAM的逻辑层、配置层、布线层进行了描述,重点介绍了逻辑层中时序控制电路和配置层中配置电路的结构和实现方法。基于0.18μm 5层金属SOI CMOS工艺完成BRAM设计实现,并对BRAM进行了仿真,功能仿真结果符合时序控制电路和配置电路的预期设计目标,性能仿真表明其工作频率可达200 MHz。     

X微处理器FPGA仿真的研究与实现

X微处理器是一款具有完全自主知识产权的通用64位高性能微处理器,规模大、复杂度高.结合X微处理器的FPGA仿真,探讨了FPGA仿真验证的技术难点:FPGA的划分、FPGA芯片引脚复用、多片FPGA芯片互连信号传输的完整性问题.提出了基于系统功能和流水线结构的FPGA划分方法与虚拟I/O技术,设计了可重配置的通用FPGA仿真板,解决了用多片FPGA芯片实现X微处理器仿真的难题.     

一种基于FPGA的嵌入式块SRAM的设计

文章中提出了一种应用于FPGA的嵌入式可配置双端口的块存储器。该存储器包括与其他电路的布线接口、可配置逻辑、可配置译码、高速读写电路。在编程状态下,可对所有存储单元进行清零,且编程后为两端口独立的双端存储器。当与FPGA其他逻辑块编程连接时,能实现FIFO等功能。基于2.5V电源电压、chart0.22μm CMOS单多晶五铝工艺设计生产,流片结果表明满足最高工作频率200MHz,可实现不同位数存储器功能。     

小型封装FPGA器件

美高森美为其主流SERDES—basedSmartFUsiOn2系统级芯片（SoC）FPGAS和IGL002FPGA器件提供全新小尺寸解决方案。这两款FPGA器件采用非易失性Flash技术,可省去外部配置存储器,为设计人员提供了极小的占位面积。新封装的推出为两种产品系列增添了多种小尺寸外型,包括FCS32511mm×11mm、VF25614mm×14mm、FCV48419mm×19mm和VQ14422mm×22mm。     

基于SRAM的FPGA互连线结构简述

FPGAs为信号处理、密码学和存储系统等领域提供了一个可编程的平台.可以在同一块芯片上配置不同的编程数据来实现相应的逻辑功能.可编程互连线资源是FPGA的重要功能模块.文中介绍了产生这种结构的原因以及层次式互连线结构是一种合理、灵活、优化的连线方式,并且对于实现电路功能、提高电路性能都有重要作用.     

延迟优化的统一可编程互连电路设计和实现

本文设计了一种对可编程逻辑单元CLB和可编程输出单元IOB均具有统一结构的可编程互连电路。通过偏移互连线和回线技术,使得同种可编程互连线的负载分布均匀,保证了可编程逻辑器件FPGA芯片中信号传输的可预测性和规整性;同时,设计过程中对编程点和驱动器电路进行专门的优化设计,减少了5%延时。运用该互连电路到实例FPGA芯片--FDP芯片中,流片后实测数据表明：该可编程互连电路中各种互连线功能正确,可以正确地完成各种信号的互连,整个芯片的延迟统一而且可预测。     

基于三维集成技术的Ku波段四通道T/R模块

基于三维集成技术研制了一款适用于表面贴装技术的Ku波段四通道T/R模块.模块内部设计成两层层叠结构,层间使用球栅阵列实现互连,仿真分析模块微波垂直互连结构、腔体谐振和散热模型,实现模块的小型化.模块集成了数控移相、数控衰减和串并转换等功能,由幅相控制多功能芯片、开关功率放大器芯片、限幅低噪声放大器和控制芯片构成.测试结果显示,在Ku波段内,单路发射通道饱和输出功率大于30 dBm,接收通道增益大于20 dB,噪声系数小于3.5 dB,模块尺寸为16 mm×16 mm×2.5 mm.     

模拟电路向FPGA学习

直到最近以前,模拟界仍然用试验电路板和全定制电路来进行设计.与数字门阵列相比,这种方法往往使原型设计周期要长达几周到几个月.这种局面现在开始发生变化,加州San Jose的International Microelectronic Products公司开发的EPAC(电可编程模拟电路)作为取代试验电路板的办法,向模拟电路设计师提供了与数字FPGA相当的设计手段.IMP50E10有丰富的模拟电路资源;只要把用户定义的配置数据存入芯片上的EEPROM配置在存储器里,就可以通过它们去控制优化的模拟开关,进而把芯片上的各种模拟电路互连起来.芯片上的模拟功能包括各种由用户编程决定的功能,如可编程增益的放大     

一种云服务器互连芯片交叉开关的设计与实现

在高端云服务器系统中,计算节点间的互连芯片通过Cache一致性协议将多计算节点互连组成分布式和共享内存空间系统,对接口传输速率和路由交换效率要求较高。文中通过分析Cache一致性协议报文的传输特点和互连网络转发需求,设计实现了一种互连芯片的高阶非对称交叉开关。设计通过了系统级的仿真验证,基于FPGA实现的云服务器互连芯片原型验证系统进行了实际带宽测试和芯片带宽匹配优化。互连芯片流片后的系统实测结果表明,满足功能要求,互连网络处理模块延迟8. 75ns,吞吐率65. 03%,达到了设计目标。     

NAND FLASH在储存测试系统中的应用

主要介绍了三星公司的NAND FLASH存储器K9K8G08UOM、以FPGA为核心模块控制K9K8G08UOM的读操作、写操作和擦除操作,以及FLASH储存器在硬件设计中的具体接法。经实际电路测量验证了其功能的正确性。     

A high-speed 1-kbit high electron mobility transistor static RAM

A 1-kbit static RAM with enhancement and depletion-mode devices was designed and fabricated using the high electron mobility transistor (HEMT) technology. The RAM circuit was optimized to achieve ultra-high-speed performance. A subnanosecond address access time of 0.6 ns was measured at room temperature for a total power dissipation of 450 mW. The minimum WRITE-ENABLE pulse width required to change the state of memory cell is less than 2 ns on probe testing. The best chip has 3 bits that failed to function, which corresponds to a bit yield of 99.7 percent. According to the simulation, variations of the threshold voltage inside the memory cell greatly reduce its stable functional range. High-speed operation requires more uniform threshold voltage control to achieve fully operational LSI memory circuits.     

一种FPGA中BRAM36k的设计方法

BRAM以阵列的方式排布于FPGA内部,是FPGA实现各种存储功能的主要部分。FPGA通过BRAM以及可编程逻辑资源给用户提供各种不同的存储资源。介绍了FPGA其中可编程存储模块BRAM36k的具体功能以及实现方法。该模块支持多种地址和数据位宽纵横比组合、多种读接口和写接口数据带宽转换,支持奇偶校验bit写入和读出。最后对模块的功能进行了功能级仿真验证,仿真结果符合预期设计目标。     

单片机技术在数据采集及监测过程中的应用

应用单片机微型智能系统对输出数据:电压、电流及电位的采集测量、显示和打印。以8031单片机为核心,8031单片机有一个8位的CPU,一个128字节的RAM,21个特殊功能寄存器,4个8位并行I/O口,1个全双工异步串行端口,2个16位定时器/计数器,5个具有优先级别的中断源。在8031外接一片程序存储器就可以构成一个有完整功能的微机应用电路。     

五位RF MEMS开关延迟线移相器

设计并研制了一种6～11GHz、超宽带5位RF MEMS开关延迟线移相器,器件实现了5位延迟:λ、2λ、4λ、8λ、16λ。该器件采用微带混合介质多层板技术,分4层制作,尺寸为45mm×20 mm。整个器件包括20个RFMEMS悬臂梁开关,用60～75V的静电压驱动。6～11GHz频带内,对32个相移态的测试结果表明:一般回波损耗S11<-10dB,各状态平均插入损耗为-8～-10dB;中心频率处,器件可实现的最大延迟位时延为1680ps,总时延为3255ps。     

A high-speed low-power Hi-CMOS 4K static RAM

A high-speed low-power CMOS fully static, 4096 word by 1 bit random-access memory (RAM) has been developed, which contains a bipolar-CMOS (BCMOS) circuit on the same chip. The device is realized using low-power-oriented circuit design and high-performance CMOS technology utilizing 3-µm gate length. The fabricated 4K static RAM has an address access time of 43 ns and a power dissipation of 80 mW.     

一种动态功能重构SRAM的设计与实现

SRAM作为常用的存储器,在速度和功耗方面有一定的优势,但其较大的面积是影响成本的主要原因。文章设计了一种256×8位动态功能重构的SRAM模块,在完成基本SRAM存储功能的前提下,通过设置重构标志信号tag及附加的控制逻辑信号,复用基本SRAM模块存储资源,使系统完成FIFO的顺序存储功能。整个设计一方面拓展了基本存储体的功能,另一方面,FPGA验证结果显示：实施重构方案后同一块FPGA器件的硬件资源利用率明显提高了。最后,采用插入门控时钟的低功耗优化方案进行了DC综合,结果显示动态功耗降低了59．6％。经过“重构”的方式后,只增加了少量电路便可以实现动态数字电路的基本功能,一方面完成了功能上的拓展,另一方面提高了存储模块硬件资源的利用率,使SRAM具有了更高的性价比。     

Dynamic reconfiguration schemes for megabit BiCMOS SRAMs and performance evaluation

In this paper two dynamic configuration schemes are discussed for megabit BiCMOS static random access memories (SRAMs). Dynamic reconfiguration schemes allows failure detection at the chip level and automatic reconfiguration to fault free memory cells within the chip. The first scheme is a standby system approach where the I/O lines of the memory can be dynamically switched to spare bit slices in the SRAM. This scheme is implemented through a switching network at the memory interface. Every memory access is controlled by a fault status table (FST) which memorizes the fault conditions of each memory block. This FST is implemented outside the memory system. A second dynamic reconfiguration scheme for BiCMOS SRAMs is addressed through a graceful degradation approach. Basic design considerations and performance evaluation of megabit BiCMOS SRAMs using dynamic reconfiguration schemes are presented. The basic properties of the proposed schemes and a prototype VLSI chip implementation details are discussed. BiCMOS SRAM access time improvement of about 35%, chip area of 25%, and chip yield of 10% are achieved, respectively, as compared to conventional methods. A comparison of reliability improvement of 1 Mb BiCMOS SRAMs using dynamic configuration schemes is presented. These two dynamic reconfiguration schemes have considerable importance in reliability improvement when compared to conventional methods. The major advantage is that the size of reconfiguration of the system can be considerably reduced.     

A submicron 1 Mbit dynamic RAM with a 4-bit-at-a-time built-in ECC circuit

A submicron CMOS 1-Mb RAM with a built-in error checking and correcting (ECC) circuit is described. An advanced bidirectional parity code with a self-checking function is proposed to reduce the soft error rate. A distributed sense circuit makes it possible to implement a small memory cell size of 20 /spl mu/m/SUP 2/ in combination with a trench capacitor technique. The 1M word/spl times/1 bit device was fabricated on a 6.4/spl times/8.2 mm chip. The additional 98-kb parity cells and the built-in ECC circuit occupy about 12% of the whole chip area. The measured access time is 140 ns, including 20 ns ECC operation.     

A 1.5-ns 256-kb BiCMOS SRAM with 60-ps 11-K logic gates

A 1.5-ns address access time, 256-kb BiCMOS SRAM has been developed. To attain this ultra-high-speed access time, an emitter-coupled logic (ECL) word driver is used to access 6-T CMOS memory cells, eliminating the ECL-MOS level-shifter time delay. The RAM uses a low-power active pull down ECL decoder. The chip contains 11-K, 60-ps ECL circuit gates. It provides variable RAM configurations and general logic functions. RAM power consumption is 18 W; chip power consumption is 35 W. The chip is fabricated by using a 0.5-μm BiCMOS process. The memory cell size is 58 μm² and the chip size is 11×11 mm     

A new circuit configuration for a single-transistor cell using Al-gate technology with reduced dimensions

A single-transistor memory cell in Al-gate technology with 2.5 /spl mu/m line width with a new circuit configuration is introduced. In this cell, the ground line of one cell and the word line of the cell opposite the bit line share the same line. This circuit configuration leads to memory cells having a bit density of 5720 bit/mm/SUP 2/ even though it uses a single layer metallization. The voltage conditions in this cell differ from those in conventional storage cells, but do not reduce the operation range of the new cell. As design and circuit studies have shown, a 32 kbit memory can be realized on a chip area of about 15.4 mm/SUP 2/, having an access time of 200 ns and a power dissipation of 500 mW.