Fabrication of micro-trench structures with high aspect ratio based on DRIE process for MEMS device applications

The micro-trench structures with high aspect ratio based on the single crystal silicon substrate are fabricated via the deep reactive ion etching (DRIE) process at different etching patterns. The relationship between the micro-trench structures and the DRIE etching patterns is investigated by simulating and processing. The micro-trench structures are obtained to meet the requirements of some MEMS devices for special applications. The profile roughness and micro-trench structures are observed by the atomic force-microscope and the field emission scanning electron microscopy. The verticality (V) of micro-trench structures is average 0.19 in the oxygen environment. The micro-trench structures exhibit better verticality, less roughness and better stability than that of no oxygen. The scalloping effects gradually decreased and the profile becomes more and more polished.     

Integrated polysilicon and DRIE bulk silicon micromachining for anelectrostatic torsional actuator

This paper presents a fabrication process that integrates polysilicon surface micromachining and deep reactive ion etching (DRIE) bulk silicon micromachining. The process takes advantage of the design flexibility of polysilicon surface micromachining and the deep silicon structures possible with DRIE. As a demonstration, a torsional actuator driven by a combdrive moving in the out-of-plane direction, consisting of polysilicon fingers and bulk silicon fingers, has been fabricated. The integrated process allows the combdrive to be integrated with any structure made by polysilicon surface micromachining     

Study of silicon backside damage in deep reactive ion etching for bonded silicon–glass structures

 For devices of bonded silicon and glass structures fabricated by deep reactive ion etching (DRIE), it is important to avoid damage at the silicon sidewall and backside during through-wafer etching in order to ensure reliability of devices. The silicon damage caused by charge accumulation at the glass surface is inhibited by means of an electrically conducting layer patterned onto the glass and connected with the silicon. In this study, indium tin oxide films were applied in order to identify the positions of silicon damage in the structural layout without destruction of samples. From the results, we report that there exists silicon damage caused by charge accumulation at the silicon islands divided by DRIE and we present important rules for mask layout when utilizing this method. Received: 10 August 2001/Accepted: 24 September 2001 This paper was presented at the Fourth International Workshop on high Aspect Ratio Microstructure Technology HARMST 2001 in June 2001.     

Fabrication of optically smooth, through-wafer silicon molds for PDMS total internal reflection-based devices

This paper presents a systematic approach to fabricate optically smooth, through-wafer silicon (Si) molds for polymer optical devices, in particular poly(dimethylsiloxane) (PDMS) total internal reflection (TIR)-based devices. First, the Si molds were fabricated by an optimized, through-wafer deep reactive ion etching (DRIE) process to achieve small roughness. To further reduce the roughness, the Si molds were then oxidized and etched in BHF for three times to achieve surface roughness average (R _a) and root mean square (RMS) roughness below 25 nm while peak-to-valley (P–V) roughness is below 150 nm. We monitored the surface roughness and morphology of the sidewalls of Si mold through three cycles of oxidation and BHF etching using field emission scanning electron microscopy (FESEM) and atomic force microscopy (AFM). We found that further oxidation and BHF etching might not have much effect in further reducing the roughness while the device feature definitions might be compromised. Finally, the PDMS TIR-based devices replicated from the Si molds were evaluated by means of FESEM, AFM and by imaging of the fluorescent evanescent spots.     

基于切割成型的侧壁表面压阻制作及其参数优化

为了提高MEMS执行器件对面内运动位移（或力学信号）检测的灵敏度并改善侧壁检测电阻制作工艺与其他工艺及其不同器件结构之间的兼容性问题,提出一种基于离子注入工艺和深度反应离子刻蚀（DRIE）工艺相结合制作检测梁侧壁压阻的方法。在此基础上,详细分析了影响位移检测灵敏度和分辨率的各种因素,并对侧壁压阻的结构尺寸及其工艺参数进行优化。最后,给出了侧壁表面压阻在几种不同类型典型MEMS执行器件中的应用,取得了很好的应用效果。     

Through wafer via holes manufacturing by variable isotropy Deep RIE process for RF applications

This paper reports a method on the manufacturing of through silicon wafer via holes with tapered walls by Deep Reactive Ion Etching using the opportunity to change the isotropy in the DRIE equipments during processing. By using consecutively anisotropic and isotropic etching steps it is possible to enlarge the dimension of via holes on one side of the wafer, while on the other side dimension is set by the initial etching window. The optimized process was used to obtain via’s with a good control over the walls angles for two etching windows sizes (100 and 20?μm respectively) on 300?μm thick silicon wafers. After process optimization, a deviation smaller than 10% of the manufactured via holes across the wafers was observed for the designed walls angles of 11.3° and 21.8°. Barrier and seed layers were deposited in via’s performed by Physical Vapor Deposition techniques with a very good coverage of the walls. Finally, gold electroplating was used to fill the narrow part of via’s.     

Vertical Mirror Fabrication Combining KOH Etch and DRIE of (110) Silicon

This paper presents fabrication of MEMS-actuated optical-quality vertical mirrors as the key active optical components in a silicon optical bench (SOB) technology. The fabrication process is based on a combination of potassium hydroxide (KOH) etch and deep reactive ion etching (DRIE) of (110) SOI wafers. The process starts by creating optical-quality vertical surfaces by KOH etch, followed by an oxidation step to protect them. The patterned wafer is then etched by DRIE to define actuators. The process is designed to allow the KOH etch and DRIE to be independently optimized without compromising either while at the same time meeting the challenge of lithography on high-aspect-ratio structures. Three variations of the fabrication process are demonstrated, two that use double masking layers and one that uses a silicon masking layer. We demonstrate in-plane scanners and fast translational vertical mirrors fabricated using these processes. In addition, we propose extensions of the fabrication process to account for DRIE aspect-ratio limitations. Mask layouts of key SOB building blocks, including vertical mirrors, beam splitters, and parallel-plate actuators, are also presented.$hfill$ [2008-0146]      

High-speed microfabricated silicon turbomachinery and fluid film bearings

A single-crystal silicon micromachined air turbine supported on gas-lubricated bearings has been operated in a controlled and sustained manner at rotational speeds greater than 1 million revolutions per minute, with mechanical power levels approaching 5 W. The device is formed from a fusion bonded stack of five silicon wafers individually patterned on both sides using deep reactive ion etching (DRIE). It consists of a single stage radial inflow turbine on a 4.2-mm diameter rotor that is supported on externally pressurized hydrostatic journal and thrust bearings. This work presents the design, fabrication, and testing of the first microfabricated rotors to operate at circumferential tip speeds up to 300 m/s, on the order of conventional high performance turbomachinery. Successful operation of this device motivates the use of silicon micromachined high-speed rotating machinery for power microelectromechanical systems (MEMS) applications such as portable energy conversion, micropropulsion, and microfluidic pumping and cooling.     

Micromachined flat-walled valveless diffuser pumps

The first valveless diffuser pump fabricated using the latest technology in deep reactive ion etching (DRIE) is presented. The pump was fabricated in a two-mask micromachining process in a silicon wafer polished on both sides, anodically bonded to a glass wafer. Pump chambers and diffuser elements were etched in the silicon wafer using DRIE, while inlet and outlet holes are etched using an anisotropic etch. The DRIE etch resulted in rectangular diffuser cross sections. Results are presented on pumps with different diffuser dimensions in terms of diffuser neck width, length, and angle. The maximum pump pressure is 7.6 m H₂O (74 kPa), and the maximum pump flow is 2.3 ml/min for water     

ICP刻蚀硅形貌控制研究

硅的刻蚀形貌控制是MEMS器件加工中的关键技术之一,形貌控制是硅表面刻蚀和钝化反应取得平衡的结果,任何影响刻蚀和钝化反应的因素都会影响到刻蚀形貌.采用中科院微电子研发中心研制的基于化学平衡原理的ICP-98A等离子刻蚀机,对ICP刻蚀当中影响形貌的关键工艺参数进行了研究和分析,研究了源功率RF1、射频功率RF2及气体(...     

微机械陀螺DRIE刻蚀过程中的局域掩膜效应

在微机电系统(MEMS)制造中,深反应离子刻蚀(DRIE)过程的精度是影响器件特性的重要因素之一.本文设计了一种完全对称弹性梁结构的模态匹配式陀螺的原型器件,以此为对象研究了局域掩膜图形对于DRIE刻蚀过程的影响.器件的测试结果表明驱动和检测模态有明显的失配,该失配的发生原因除了气体阻尼,更主要来源于驱动和检测结构弹性梁尺寸的工艺偏差.在分析了实验过程及结果的基础上可以认为,除了典型的DRIE滞后效应等因素外,器件结构的局域掩膜效应加剧了工艺偏差:对称弹性梁结构周边的非对称掩膜图形导致了刻蚀气体分布的局部不均匀,增加了DRIE刻蚀的侧蚀偏差.     

一种新结构硅微机械压阻加速度计

设计、制造并测试了一种新结构硅微机械压阻加速度计.器件结构是悬臂梁-质量块结构的一种变形.比较硬的主悬臂梁提供了一定的机械强度,并且提供了高谐振频率.微梁很细,检测时微梁沿轴向直拉直压.力敏电阻就扩散在微梁上,质量块很小的挠动就能在微梁上产生很大的应力,输出很大的信号.5 V条件下,灵敏度为14.80 mV/g,谐振频率为994 Hz,分别是传统结构压阻加速度计的2.487倍和2.485倍.加速度计用普通的N型硅片制造,为了刻蚀高深宽比的结构,使用了深反应离子刻蚀(DRIE)工艺.     

ICP深硅刻蚀工艺掩模的研究

通过使用深硅等离子刻蚀机,以C4 F8和SF6为刻蚀气体,对以光刻胶与金属铝两种材料作为掩模的深硅刻蚀结果进行对比,研究了深硅刻蚀过程中掩模材料对刻蚀结果的影响。实验结果表明：以光刻胶做掩模,深硅刻蚀后硅侧壁和硅底部表面形貌平整,垂直度较之铝掩模相当;以金属铝做掩模,深硅刻蚀后深槽底部表面不平整,出现长草现象,但是刻蚀选择比大于光刻胶,两种掩模的硅刻蚀速率相当。     

Microfabrication of high-temperature silicon devices using waferbonding and deep reactive ion etching

As part of an effort to develop a micro gas turbine engine capable of providing 10-50 W of electrical power in a package less than one cubic centimeter in volume, we report the fabrication and testing of the first hydrogen combustor micromachined from silicon. Measuring 0.066 cm ³ in volume, and complete with a fuel manifold and set of fuel injector holes, the fabrication of the device was largely enabled by the use of deep reactive ion etching (DRIE) and aligned silicon wafer bonding. The 150-W microcombustor has a power density in excess of 2000 MW/m³ and has been successfully demonstrated to provide turbine inlet temperatures up to 1800 K. After 15 h of experimental tests, the combustor maintained its mechanical integrity and did not exhibit any visible damage. Combined with the results of a materials oxidation study, these tests are used to demonstrate the satisfactory performance of silicon in the harsh oxidizing environment of a combustion chamber     

基于金硅原电池保护电容加速度计的制作

提出并实现了一种利用SoI结合金硅原电池保护和反熔丝制作电容式加速度计的新工艺方法。该工艺用SoI顶层硅制作梁和上电极,用衬底制作质量块。采用DRIE从正面刻蚀形成释放孔,TMAH腐蚀实现质量块的释放,在TMAH腐蚀过程中利用金硅原电池保护实现梁和表面极板的保护。在TMAH腐蚀完成前,反镕丝保持断开状态,腐蚀完成后,击穿反镕丝形成导通状态。通过测量金和硅的极化曲线得到60℃25%TMAH中实现原电池保护的金硅面积比不小于5∶1。成功制作成电容式加速度计结构,释放前后梁宽度均在9.4～10μm范围内,表明原电池保护有效。击穿后反熔丝并联导通电阻为5～25 kΩ之间。     

Layout controlled one-step dry etch and release of MEMS using deep RIE on SOI wafer

Deep reactive ion etching (DRIE) of silicon on insulator (SOI) wafer has become a popular method to build microelectromechanical systems (MEMS) because it is versatile and simple. However when the devices using this technology become large in size or have compliant beams, the stiction occurring during the HF wet release is a serious problem. We have observed that some structure patterns could be wet released more easily than others. In this paper, we discuss the relationship between structure patterns and their stiction property, and describe the notching effect, which is found to be the mechanism behind this dependence. We finally provide simple mask layout design rules to utilize this effect to our advantage. These rules allow etching the structure and releasing it with the same DRIE step, without any wet process. Alternatively, this method will completely remove the stiction appearing during wet release or other further wet processes. We show the application of these rules on the fabrication of a large moving stage.     

Towards a versatile DRIE: silicon pit structures combined with electrochemical etch stop

A novel approach for fabricating low-pitch arrays of silicon membranes on standard CMOS wafers by combining deep-reactive ion etching (DRIE) and electrochemical etching (ECE) techniques is presented. These techniques have been used to fabricate membrane-based sensors and sensor arrays featuring different membrane sizes on a single wafer with a well defined etch stop. The described procedure is particularly useful in cases when the usage of SOI wafers is not an option. The combination of a grid-like mask pattern featuring uniform-size etch openings for the DRIE process with a reliable ECE technique allowed to fabricate silicon membranes with sizes ranging from 0.01 mm/sup 2/ to 2.2 mm/sup 2/. The development of this new method has been motivated by the need to design a compact n-well-based calorimetric sensor array, where the use of a standard ECE technique would have significantly increased the overall size of the device.     

Integration of Trench-Isolated Through-Wafer Interconnects with 2D Capacitive Micromachined Ultrasonic Transducer Arrays

This paper presents a method to provide electrical connection to a 2D capacitive micromachined ultrasonic transducer (CMUT) array. The interconnects are processed after the CMUTs are fabricated on the front side of a silicon wafer. Connections to array elements are made from the back side of the substrate via highly conductive silicon pillars that result from a deep reactive ion etching (DRIE) process. Flip-chip bonding is used to integrate the CMUT array with an integrated circuit (IC) that comprises the front-end circuits for the transducer and provides mechanical support for the trench-isolated array elements. Design, fabrication process and characterization results are presented. The advantages when compared to other through-wafer interconnect techniques are discussed.     

Process development of precision surface micro-machining using mechanical abrasion and chemical etching

 A process that is capable of micro-machining the surface of both metallic and silicon materials has been developed. The process is based on mechanical abrasion of the surface using a very sharp and hard tool followed by chemical etching in some instances. The most critical parameter for the mechanical abrasion process is the thrust force which essentially dictates the mode of cutting. Experiments were performed using a specially built precision programmable machine with sub-micrometer feed resolution to identify the optimum operating conditions to obtain satisfactory cutting. By carefully adjusting the feed of the tool, pockets could also be machined quite successfully. In order to demonstrate the flexibility of the process, a miniature face was machined on both silicon and brass. The micro-machining process presented in this work can also be used to fabricate micro-molds as well as micro-grooves. Received: 24 August 2001/Accepted: 7 November 2001