640像素×480像素CMOS图像传感器

飞利浦半导体公司推出了640像素×480像素CMOS图像传感器,该产品采用32管脚的小型CLCC(ceramic leaded chip carrier)封装。产品名为“UPA1021”。电源电压为 3.3V,30帧/秒输出数据时的消耗功率为75mW,待机模式时的消耗功率小于1mW。产品配备9bit A-D转换器。 UPA1021的光传感器部分大小只有5.6μm×5.6μm,从而可将芯片缩小到能够     

高帧频面阵CCD探测器应用技术研究

分析了高帧频帧转移面阵CCD的工作机制,设计了驱动电路和信号处理电路,获得了帧频为130帧/秒的高清晰图像,并提出了一种采用遮光板来提高帧频的新方法.该方法将帧频提高到了400帧/秒,具有较高的有效曝光比,并进一步改善了图像的质量.     

基于FPGA的大面阵CCD高帧频驱动电路设计

介绍了Dalsa公司的33M像素大面阵CCD的内部结构,着重分析了该款CCD的驱动时序.针对大面阵CCD图像传感器帧频较低的缺点,设计了基于现场可编程逻辑门阵列的驱动电路.改进了CCD芯片的偏置电压电路,提出了4 路同时输出以提高帧频的电路设计方法,最高帧频可达2.7帧/s ,相比单端输出时的0.7帧/s提高了约4倍.选用FPGA作为核心器件,使用VHDL语言设计驱动时序,在ISE和Modelsim环境下对所设计的驱动时序发生器进行仿真实验.实验结果表明,所设计的驱动电路能够满足大面阵CCD高帧频应用.     

采集高速扫描数据的高帧频电视

用于采集高速扫描数据的高帧频电视,是一种专用的闭路电视,它的帧频高于广播电视的帧频(25帧/秒或30帧/秒).本文介绍的是一种帧频为200帧/秒、扫描线数为250线的高帧频电视;并根据高帧频电视的特点,对摄象管的选择、电路的特点和设计考虑、整机的性能作了较详细的说明.     

ViTA 1300：通用CMOS图像传感器

赛普拉斯推出一款面向机器视觉市场的高灵敏度高速CMOS图像传感器。该款全新的130万像素VITA1300传感器结合了管线式和触发式全局快门,具有150帧,秒（fps）的无图像畸变高帧频,而且读出速度很快。     

Aptina推出APS-C格式1600万像素图像传感器

Aptina近日推出其高性能、功能丰富、APS-C格式的1600万像素的图像传感器。特别的设计令该产品可实现专业摄影师所要求的高画质,除了以10帧/秒的速度捕捉1600万像素的静态图像以外,     

产品撷英

挑战CCD的百万像素CMOS图像传感器3百万图像传感器以较低的功耗提供高分辨率 CMOS Color Capture Device（C3D）的像素密度是同类产品的3倍,是首个采用3,3μm像素,0.25μ m点距的CMOS图像传感器,分辨率达2056×1544,其图像质量足以匹敌高分辨率数码相机中的CCD,而消耗的功率则要少得多。 器件独特的像素结构包括为增加动态范围而设计的电路、更好的灵敏度和一致性,以及更小的噪声,视频速率为30fps,暗电流密度为1nA/cm2,动态范围为62dB,拍摄静止图像和全速率视频图像时的功耗分别为200mW和275mw。 Y Media marketing@y-media.com http://www.y-media.com     

Micron 130万像素传感器瞄准快速发展的手机市场

Micron科技有限公司宣布推出MT9M011 130万像素传感器。该新品特别针对包括智能手机和3G手机平台等中、高端移动市场而设计。通过充分运用其150nm低漏DRAM工艺和开发一种利用这些工艺的独特传感器体系结构,使得该新品能达到基于CCD传感器灵敏度水平的低光照性能。MT9M011还包括可编程的增益控制、曝光控制和黑标准校正等特性,可以在保持流畅、连续的动态图像的同时,在50mW的功耗下,以最高30帧/秒的帧率,进行任意大小的图像捕捉。同时,该公司还宣布向移动影像市场推出两款高等级的VGA DigitalClarity CMOS图像传感器——MT9V011…     

光电器件

每秒可捕捉2万帧图像的超高速CMOS图像传感器 它的象元有640×480个,当所有16个输出口都用于输出全帧图像时,波传感器具有每秒1500帧的采集能力。它还采用了特殊的多路复用器,可实     

像素内两次曝光组合的宽动态范围CMOS图像传感器

提出了一种基于五管有源像素的宽动态范围CMOS图像传感器（CIS）,在像素内部的浮动节点处进行长曝光时间信号和短曝光时间信号的组合。通过优化像素操作,光电响应曲线得到了压缩,获得了宽动态范围图像。设计的CMOS图像传感器采用0.18μm CIS工艺进行了流片,测试结果表明在两次曝光时间分别为2.4ms和70ns,30帧每秒的帧频条件下,传感器的动态范围达到80dB,满足安防监视系统的应用需求。     

A single-chip CMOS APS camera with direct frame difference output

A complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) camera chip with direct frame difference output is reported in this paper. The proposed APS cell circuit has in-pixel storage for previous frame image data so that the current frame image and the previous frame image can be read out simultaneously in differential mode. The signal swing of the pixel circuit is maximized for low supply voltage operation. The pixel circuit occupies 32.2×32.2 μm² of chip area with a fill factor of 33%. A 128×98 element prototype camera chip with an on-chip 8-bit analog-to-digital converter has been fabricated in a 0.5-μm double-poly double-metal CMOS process and successfully tested. The camera chip consumes 56 mW at 30 frames/s with 3.3 V power supply     

A 10000 frames/s CMOS digital pixel sensor

A 352×288 pixel CMOS image sensor chip with per-pixel single-slope ADC and dynamic memory in a standard digital 0.18-μm CMOS process is described. The chip performs "snapshot" image acquisition, parallel 8-bit A/D conversion, and digital readout at continuous rate of 10000 frames/s or 1 Gpixels/s with power consumption of 50 mW. Each pixel consists of a photogate circuit, a three-stage comparator, and an 8-bit 3T dynamic memory comprising a total of 37 transistors in 9.4×9.4 μm with a fill factor of 15%. The photogate quantum efficiency is 13.6%, and the sensor conversion gain is 13.1 μV/e^-. At 1000 frames/s, measured integral nonlinearity is 0.22% over a 1-V range, rms temporal noise with digital CDS is 0.15%, and rms FPN with digital CDS is 0.027%. When operated at low frame rates, on-chip power management circuits permit complete powerdown between each frame conversion and readout. The digitized pixel data is read out over a 64-bit (8-pixel) wide bus operating at 167 MHz, i.e., over 1.33 GB/s. The chip is suitable for general high-speed imaging applications as well as for the implementation of several still and standard video rate applications that benefit from high-speed capture, such as dynamic range enhancement, motion estimation and compensation, and image stabilization     

A new CMOS pixel structure for low-dark-current and large-array-size still imager applications

A pixel structure for still CMOS imager application called the pseudoactive pixel sensor (PAPS) is proposed and analyzed in this paper. It has the advantages of a low dark current, high signal-to-noise ratio, and a high fill factor over the conventional passive pixel sensor imager or active pixel sensor imager. The readout circuit called the zero-bias column buffer-direct-injection structure is also proposed to suppress both the dark current of the photodiode and the leakage current of row switches by keeping both biases of photodiode and the parasitic p-n junction in the column bus at or near zero voltage. The improved double delta sampling circuits are also used to suppress fixed pattern noise, clock feedthrough noise, and channel charge injection. An experimental chip of the proposed PAPS CMOS imager with the format of 352/spl times/288 (CIF) has been fabricated by using a 0.25-/spl mu/m single-poly-five-level-metal (1P5M) n-well CMOS process. The pixel size is 5.8 /spl mu/m/spl times/5.8 /spl mu/m. The pixel readout speed is from 100 kHz to 10 MHz, corresponding to the maximum frame rate above 30 frames/s. The proposed still CMOS imager has a fill factor of 58%, chip size of 3660 /spl mu/m/spl times/3500 /spl mu/m, and power dissipation of 24 mW under the power supply of 3.3 V. The experimental chip has successfully demonstrated the function of the proposed new PAPS structure. It can be applied in the design of large-array-size still CMOS imager systems with a low dark current and high resolution.     

A 10 000 fps CMOS Sensor With Massively Parallel Image Processing

A high-speed analog VLSI image acquisition and pre-processing system has been designed and fabricated in a 0.35 mum standard CMOS process. The chip features a massively parallel architecture enabling the computation of programmable low-level image processing in each pixel. Extraction of spatial gradients and convolutions such as Sobel or Laplacian filters are implemented on the circuit. For this purpose, each 35 mum times 35 mum pixel includes a photodiode, an amplifier, two storage capacitors, and an analog arithmetic unit based on a four-quadrant multiplier architecture. The retina provides address-event coded output on three asynchronous buses: one output dedicated to the gradient and the other two to the pixel values. A 64 times 64 pixel proof-of-concept chip was fabricated. A dedicated embedded platform including FPGA and ADCs has also been designed to evaluate the vision chip. Measured results show that the proposed sensor successfully captures raw images up to 10 000 frames per second and runs low-level image processing at a frame rate of 2000 to 5000 frames per second.     

A low power dissipation high-speed CMOS image sensor with column-parallel sigma–delta ADCs

A 60frames/s CMOS image sensor with column-parallel inverter-based sigma–delta (ΣΔ) ADCs is proposed in this paper. In order to improve the robustness of the inverter, instead of constant power supply, two buffers are designed to provide power supply for inverters. Instead of using of an operational amplifier, an inverter-based switch-capacitor (SC) circuit is adopted to low-voltage low-power ΣΔ modulator. Detailed analysis and design optimization are provided. Due to the use of the inverter-based ΣΔ ADCs, the conversion speed is improved while reducing the area and power consumption. The proposed CMOS image sensor has been fabricated with 0.18 μm CMOS process. The measurement results show that the random noise (RN) is 7e_rms⁻, the pixel conversion gain is 100 μV/e⁻. Since the measured full well capacity of the pixel is 25000e⁻, the CMOS image sensor achieves a 71 dB dynamic range (DR). The total power consumption at 60frame/s is 58.2 mW.     

A Nyquist-rate pixel-level ADC for CMOS image sensors

A multichannel bit-serial (MCBS) analog-to-digital converter (ADC) is presented. The ADC is ideally suited to pixel-level implementation in a CMOS image sensor. The ADC uses successive comparisons to output one bit at a time simultaneously from all pixels. It is implemented using a 1-bit comparator/latch pair per pixel or per group of neighboring pixels, and a digital-to-analog-converter/controller shared by all pixels. The comparator/latch pair operates at very slow speeds and can be implemented using simple robust circuits. The ADCs can be fully tested by applying electrical signals without any optics or light sources. A CMOS 320×256 sensor using the MCBS ADC is described. The chip measures 4.14×5.16 mm². It achieves 10×10 μm² pixel size at 28% fill factor in 0.35 μm CMOS technology. Each 2×2 pixel block shares an ADC. The pixel block circuit comprises 18 transistors. It operates in subthreshold to maximize gain and minimize power consumption. The power consumed by the sensor array is 20 mW at 30 frames/s. The measured integral nonlinearity is 2.3 LSB, and differential nonlinearity is 1.2 LSB at eight bits of resolution. The standard deviation of the gain and offset fixed pattern noise due to the ADC are 0.24 and 0.2%, respectively     

A 1.25-inch 60-frames/s 8.3-M-pixel digital-output CMOS image sensor

The ultrahigh-definition television (UDTV) camera system requires an image sensor having four times higher resolution and two times higher frame rate than the conventional HDTV systems. Also, an image sensor with a small optical format and low power consumption is required for practical UDTV camera systems. To respond to these requirements, we have developed an 8.3-M-pixel digital-output CMOS active pixel sensor (APS) for the UDTV application. It features an optical format of 1.25inch, low power consumption of less than 600 mW at dark, while reproducing a low-noise, 60-frames/s progressive scan image. The image sensor is equipped with 1920 on-chip 10-bit analog-to-digital converters and outputs digital data stream through 16 parallel output ports. Design considerations to reproduce a low-noise, high-resolution image at high frame rate of 60 fps are described. Implementation and experimental results of the 8.3-M-pixel CMOS APS are presented.     

An Activity-Triggered 95.3 dB DR $-$75.6 dB THD CMOS Imaging Sensor With Digital Calibration

Imaging sensors are being used as data acquisition systems in new biomedical applications. These applications require wide dynamic range (WDR), high linearity and high signal-to-noise ratio (SNR), which cannot be met simultaneously by existing CMOS imaging sensors. This paper introduces a new activity-triggered WDR CMOS imaging sensor with very low distortion. The new WDR pixel includes self-resetting circuits to partially quantize the photocurrent in the pixel. The pixel residual analog voltage is further quantized by a low-resolution column-wise ADC. The ADC code and the partially quantized pixel codes are processed by column-wise digital circuits to form WDR images. Calibration circuits are included in the pixel to improve the pixel linearity by a digital calibration method, which requires low calibration overhead. Current-mode difference circuits are included in the pixel to detect activities within the scene so that the imaging sensor captures high quality images only for scenes with intense activity. A proof-of-concept 32 times 32 imaging sensor is fabricated in a 0.35 mum CMOS process. The fill factor of the new pixel is 27%. Silicon measurements show that the new imaging sensor can achieve 95.3 dB dynamic range with low distortion of -75.6 dB after calibration. The maximum SNR of the sensor is 74.5 dB. The imaging sensor runs at frame rate up to 15 Hz.     

A CMOS Image Sensor for Multi-Level Focal Plane Image Decomposition

An alternative image decomposition method that exploits prediction via nearby pixels has been integrated on the CMOS image sensor focal plane. The proposed focal plane decomposition is compared to the 2-D discrete wavelet transform (DWT) decomposition commonly used in state of the art compression schemes such as SPIHT and JPEG2000. The method achieves comparable compression performance with much lower computational complexity and allows image compression to be implemented directly on the sensor focal plane in a completely pixel parallel structure. A CMOS prototype chip has been fabricated and tested. The test results validate the pixel design and demonstrate that lossy prediction based focal plane image compression can be realized inside the sensor pixel array to achieve a high frame rate with much lower data readout volume. The features of the proposed decomposition scheme also benefit real-time, low rate and low power applications.      

A single-chip optical sensor with analog memory for motiondetection

A 64×64-pixel image sensor with full-frame analog memory and on-chip motion processor is presented. The processor consists of a charge amplifier and an analog subtractor. It uses the switched-capacitor technique and calculates the difference between the values of the signal on each pixel in successive frames. The rate can achieve up to 60 frames/s with limited area and power overhead. The analog memory required for the storage of the previous frame is implemented using implanted capacitors placed within the sensor array. Fabricated in a 1.2-μm standard CMOS process with an added metal 3 light-shielding layer, the circuit is fully functional and requires a total core area of 13 mm²